TI TPS65982DMC：坞站管理控制器技术详情

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"TI-TPS65982DMC.pdf" TI公司的TPS65982DMC是一款针对坞站管理设计的高性能控制器，适用于Thunderbolt 4设备、USB4器件、扩展坞及监视器等应用。该控制器具备多种关键功能，旨在优化坞站电源管理和连接控制。 1. 安全固件更新：TPS65982DMC支持通过USB低速接口进行安全的固件更新，确保了TPS65982DMC以及其他TIPD控制器的固件能够得到及时且安全的更新。更新过程采用SHA-256和RSA-3072加密算法进行身份验证，保证了固件的安全性。同时，该控制器还支持不安全固件更新的处理。 2. 桶形插孔输入控制：内置的NFET栅极驱动器能监控和控制输入电源，具备过压检测功能，确保设备在异常电压条件下的安全。软启动功能则有助于防止电流冲击，保护电路。 3. 智能电源策略管理：TPS65982DMC能够智能管理坞站内的所有电源，包括USB Type-C、USB Type-A和系统电源。其可配置的智能电源策略管理器可以根据不同应用场景自动调整电源分配。 4. USB4连接管理：当UFP（通用功能设备）主机连接变化时，该控制器可以更新DFP（下游端口）端口配置，重新配置PD控制器，并发送正确的连接更改通知。此外，它还提供可配置的GPIO，供系统使用。 5. 封装技术：采用NFBGA封装，0.5mm间距，所有引脚均兼容通孔，适应性强，便于集成到各种硬件设计中。该控制器通过I2C接口与系统通信，并且包含一个3.3V的D+/D-接口，以及USB2.0端点和广告牌功能，可以接收来自外部适配器的固件更新。外部内存通过SPI接口连接，用于存储固件。简化的系统连接图显示了TPS65982DMC如何与各个组件交互，以实现高效的坞站管理。在USB4系统中，TPS65982DMC监测上行端口的状态，确保下行端口的连接状态与之同步，从而保持数据传输的一致性。此外，它还监控系统中的电流，调整PD控制器的功率通告，防止外部适配器过载。 TPS65982DMC是现代坞站解决方案的关键组成部分，提供高效、安全的电源管理与连接控制，以满足高带宽、高速度的USB4和Thunderbolt 4设备的需求。

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SWDIO

SWDIO_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V

SWDIO_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V

SWDIO_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2 V

SWDIO_ILKG Leakage current Output is Hi-Z, V

= 0 to LDO_3V3

–1

μA

SWDIO_VOH Output high voltage

= –8 mA, LDO_3V3 = 3.3 V

2.9 V

= –15 mA, LDO_3V3 = 3.3 V

2.5

SWDIO_VOL Output low voltage

= 10 mA 0.4 V

= 20 mA 0.8

SWDIO_RPU Pullup resistance

2.8 4 5.2

kΩ

SWDIO_TOS SWDIO output skew to falling edge SWDCLK

–5

5 ns

SWDIO_TIS

Input setup time required between SWDIO and rising

edge of SWCLK

6 ns

SWDIO_TIH

Input hold time required between SWDIO and rising edge

of SWCLK

1 ns

SWDCLK

SWDCL_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V

SWDCL_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V

SWDCL_THI SWDIOCLK HIGH period

0.05 500

μs

SWDCL_TLO SWDIOCLK LOW period

0.05 500

μs

SWDCL_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V

SWDCL_RPU Pullup resistance

2.8 4 5.2

kΩ

GPIO, MRESET, RESETZ, ADP_POWER_CFG

GPIO_VIH High-level input voltage

LDO_3V3 = 3.3 V 2 V

VDDIO = 1.8 V 1.25

GPIO_VIL Low-level input voltage

LDO_3V3 = 3.3 V 0.8

VDDIO = 1.8 V 0.63

GPIO_HYS Input hysteresis Voltage

LDO_3V3 = 3.3 V 0.2

VDDIO = 1.8 V 0.09

GPIO_ILKG I/O leakage current INPUT = 0 V to VDD

–1

μA

GPIO_RPU Pullup resistance Pullup enabled 50 100 150

kΩ

GPIO_RPD Pulldown resistance Pulldown enabled 50 100 150

kΩ

GPIO_DG Digital input path deglitch 20 ns

GPIO_VOH GPIO output high voltage

= –2 mA, LDO_3V3 = 3.3 V

2.9

= –2 mA, VDDIO = 1.8 V

1.35

GPIO_VOL GPIO output low voltage

= 2 mA, LDO_3V3 = 3.3 V 0.4

= 2 mA, VDDIO = 1.8 V 0.45

HRESET

HRESET_VIH High-level input voltage 1.25 V

HRESET_VIL Low-level input voltage 0.63 V

HRESET_HYS Input hysteresis Voltage .09 V

HRESET_ILKG I/O leakage current INPUT = 0 V to LDO_1V8D

–1

μA

HRESET_THIGH HRESET minimum high time to assert a reset condition. 2.0

HRESET_TLOW

HRESET minimum low time to deassert a reset

condition.

2.0

TPS65982DMC

ZHCSLZ6 – SEPTEMBER 2020

www.ti.com.cn

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Product Folder Links: TPS65982DMC

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SDA and SCL FAST MODE CHARACTERISTICS

FSCL I

C clock frequency 0 400 kHz

THIGH I

C clock high time 0.6

μs

TLOW I

C clock low time 1.3

μs

TSUDAT I

C serial data setup time 100 ns

THDDAT I

C serial data hold time 0 ns

TVDDAT I

C Valid data time SCL low to SDA output valid 0.9

μs

TVDACK I

C Valid data time of ACK condition

ACK signal from SCL low to SDA (out)

low

0.9

μs

TOCF I

C output fall time

10-pF to 400-pF bus, VDD = 3.3 V 12 250

10-pF to 400-pF bus, VDD = 1.8 V 6.5 250

TBUF I

C bus free time between stop and start 1.3

μs

TSTS I

Cstart or repeated Start condition setup time 0.6

μs

TSTH I

C Start or repeated Start condition hold time 0.6

μs

TSPS I

C Stop condition setup time 0.6

μs

6.12 SPI Master Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

FSPI Frequency of SPI_CLK 11.82 12 12.18 MHz

TPER Period of SPI_CLK (1/F_SPI) 82.1 83.33 84.6 ns

TWHI SPI_CLK High Width 30 ns

TWLO SPI_CLK Low Width 30 ns

TDACT SPI_SZZ falling to SPI_CLK rising delay time 30 50 ns

TDINACT SPI_CLK falling to SPI_SSZ rising delay time 160 180 ns

TDMOSI SPI_CLK falling to SPI_MOSI Valid delay time

–5

5 ns

TSUMISO SPI_MISO valid to SPI_CLK falling setup time 21 ns

THDMSIO SPI_CLK falling to SPI_MISO invalid hold time 0 ns

TRSPI SPI_SSZ/CLK/MOSI rise time

10% to 90%, C

= 5 pF to 50 pF,

LDO_3V3 = 3.3 V

0.1 8 ns

TFSPI SPI_SSZ/CLK/MOSI fall time

90% to 10%, C

= 5 pF to 50 pF,

LDO_3V3 = 3.3 V

0.1 8 ns

6.13 Single-Wire Debugger (SWD) Timing Requirements

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

FSWD Frequency of SWD_CLK 10 MHz

TPER Period of SWD_CLK (1/FSWD) 100 ns

TWHI SWD_CLK High Width 35 ns

TWLO SWD_CLK Low Width 35 ns

TDOUT SWD_CLK rising to SWD_DATA valid delay time 2 25 ns

TSUIN SWD_DATA valid to SWD_CLK rising setup time 9 ns

THDIN SWD_DATA hold time from SWD_CLK rising 3 ns

TRSWD SWD Output rise time

10% to 90%, C

= 5 pF to 50 pF,

LDO_3V3 = 3.3 V

0.1 8

TFSWD SWD Output fall time

90% to 10%, C

= 5 pF to 50 pF,

LDO_3V3 = 3.3 V

0.1 8

TPS65982DMC

ZHCSLZ6 – SEPTEMBER 2020

www.ti.com.cn

12 Submit Document Feedback

Product Folder Links: TPS65982DMC

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TI TPS65982DMC：坞站管理控制器技术详情

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