Intel PIIX4: PCI-ISA-IDE桥接器技术规格

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"82371AB PCI-TO-ISA-IDE Xcelerator (PIIX4) Datasheet.pdf 是一份关于Intel 82371AB芯片的详细技术文档，该芯片是一款多功能的PCI到ISA桥接器，主要用于 Pentium及Pentium II微处理器的系统中。文档描述了其特性、支持的功能以及电源管理逻辑等关键信息。" Intel的82371AB芯片，也称为PIIX4，是一款设计用于加速PCI到ISA和IDE接口通信的控制器。这款芯片的关键特性包括： 1. **多功能PCI到ISABridge**：它能够连接PCI总线和ISA（Industry Standard Architecture）或EIO（Extended I/O）总线，允许不同总线间的高效数据传输。 2. **支持PCI标准**：芯片兼容30MHz和33MHz频率的PCI规范2.1版，确保与当时主流的PCI设备兼容。 3. **ISA和EIO支持**：PIIX4支持全速ISA和EIO总线，且能以PCI频率的1/4运行这两种总线，提高了低速设备的性能。 4. **地址解码方式**：芯片支持全正解码和减法解码两种方式来处理PCI的地址空间，提供了灵活性以适应不同的系统配置。 5. **适用于移动和桌面环境**：82371AB采用3.3V操作，具有5V容限缓冲器，特别适合低功耗的移动设备，并包含针对移动环境的超低功耗设计。 6. **电源管理**：该芯片集成有电源管理逻辑，如电源-on暂停、暂停到RAM、暂停到磁盘以及软关闭系统状态。所有寄存器都可读取并恢复，确保从0V暂停状态下正确恢复。 7. **热报警和支持外部微控制器**：具备热报警功能，可以监控系统温度，同时支持外部微控制器进行更高级的系统管理。 8. **全面的ACPI支持**：支持Advanced Configuration and Power Interface（ACPI）1.0规范，实现了操作系统导向的电源管理，使得系统可以根据需求动态调整能耗。 9. **IDE控制器集成**：PIIX4还集成了IDE控制器，对硬盘和其他IDE设备的控制进行了优化，提高了IDE设备的性能。 Intel 82371AB PIIX4是90年代末期高性能个人电脑系统中重要的组成部分，它通过优化总线通信和智能电源管理，提升了系统的整体效能和便携性。这份 datasheet 提供了深入的技术细节，对理解和开发基于此芯片的系统设计非常有价值。

82371AB (PIIX4) E

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

2.1. PIIX4 Signals

2.1.1. PCI BUS INTERFACE

Name Type Description

AD[31:0] I/O PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first

clock of a transaction, AD[31:0] contain a physical byte address (32 bits). During

subsequent clocks, AD[31:0] contain data.

A PIIX4 Bus transaction consists of an address phase followed by one or more data

phases. Little-endian byte ordering is used. AD[7:0] define the least significant byte

(LSB) and AD[31:24] the most significant byte (MSB).

When PIIX4 is a Target, AD[31:0] are inputs during the address phase of a transaction.

During the following data phase(s), PIIX4 may be asked to supply data on AD[31:0] for

a PCI read, or accept data for a PCI write.

As an Initiator, PIIX4 drives a valid address on AD[31:2] and 0 on AD[1:0] during the

address phase, and drives write or latches read data on AD[31:0] during the data

phase.

During Reset: High-Z After Reset: High-Z During POS: High-Z

C/BE#[3:0] I/O BUS COMMAND AND BYTE ENABLES. The command and byte enable signals are

multiplexed on the same PCI pins. During the address phase of a transaction,

C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as

Byte Enables. The Byte Enables determine which byte lanes carry meaningful data.

C/BE0# applies to byte 0, C/BE1# to byte 1, etc. PIIX4 drives C/BE[3:0]# as an Initiator

and monitors C/BE[3:0]# as a Target.

During Reset: High-Z After Reset: High-Z During POS: High-Z

CLKRUN# I/O CLOCK RUN#. This signal is used to communicate to PCI peripherals that the PCI

clock will be stopped. Peripherals can assert CLKRUN# to request that the PCI clock

be restarted or to keep it from stopping. This function follows the protocol described in

the PCI Mobile Design Guide, Revision 1.0.

During Reset: Low After Reset: Low During POS: High

DEVSEL# I/O DEVICE SELECT. PIIX4 asserts DEVSEL# to claim a PCI transaction through positive

decoding or subtractive decoding (if enabled). As an output, PIIX4 asserts DEVSEL#

when it samples IDSEL active in configuration cycles to PIIX4 configuration registers.

PIIX4 also asserts DEVSEL# when an internal PIIX4 address is decoded or when PIIX4

subtractively or positively decodes a cycle for the ISA/EIO bus or IDE device. As an

input, DEVSEL# indicates the response to a PIIX4 initiated transaction and is also

sampled when deciding whether to subtractively decode the cycle. DEVSEL# is tri-

stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated until driven by

PIIX4 as a target.

During Reset: High-Z After Reset: High-Z During POS: High-Z

FRAME# I/O CYCLE FRAME. FRAME# is driven by the current Initiator to indicate the beginning and

duration of an access. While FRAME# is asserted data transfers continue. When

FRAME# is negated the transaction is in the final data phase. FRAME# is an input to

PIIX4 when it is the Target. FRAME# is an output when PIIX4 is the initiator. FRAME#

remains tri-stated until driven by PIIX4 as an Initiator.

During Reset: High-Z After Reset: High-Z During POS: High-Z

E 82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

Name Type Description

IDSEL I INITIALIZATION DEVICE SELECT. IDSEL is used as a chip select during PCI

configuration read and write cycles. PIIX4 samples IDSEL during the address phase of

a transaction. If IDSEL is sampled active, and the bus command is a configuration read

or write, PIIX4 responds by asserting DEVSEL# on the next cycle.

IRDY# I/O INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete the

current data phase of the transaction. It is used in conjunction with TRDY#. A data

phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During

a write, IRDY# indicates PIIX4 has valid data present on AD[31:0]. During a read, it

indicates PIIX4 is prepared to latch data. IRDY# is an input to PIIX4 when PIIX4 is the

Target and an output when PIIX4 is an Initiator. IRDY# remains tri-stated until driven by

PIIX4 as a master.

During Reset: High-Z After Reset: High-Z During POS: High-Z

PAR O CALCULATED PARITY SIGNAL. PAR is “even” parity and is calculated on 36 bits;

AD[31:0] plus C/BE[3:0]#. “Even” parity means that the number of “1”s within the

36 bits plus PAR are counted and the sum is always even. PAR is always calculated on

36 bits regardless of the valid byte enables. PAR is generated for address and data

phases and is only guaranteed to be valid one PCI clock after the corresponding

address or data phase. PAR is driven and tri-stated identically to the AD[31:0] lines

except that PAR is delayed by exactly one PCI clock. PAR is an output during the

address phase (delayed one clock) for all PIIX4 initiated transactions. It is also an

output during the data phase (delayed one clock) when PIIX4 is the Initiator of a PCI

write transaction, and when it is the Target of a read transaction.

During Reset: High-Z After Reset: High-Z During POS: High-Z

PCIRST# O PCI RESET. PIIX4 asserts PCIRST# to reset devices that reside on the PCI bus. PIIX4

asserts PCIRST# during power-up and when a hard reset sequence is initiated through

the RC register. PCIRST# is driven inactive a minimum of 1 ms after PWROK is driven

active. PCIRST# is driven for a minimum of 1 ms when initiated through the RC register.

PCIRST# is driven asynchronously relative to PCICLK.

During Reset: Low After Reset: High During POS: High

PHOLD# O PCI HOLD. An active low assertion indicates that PIIX4 desires use of the PCI Bus.

Once the PCI arbiter has asserted PHLDA# to PIIX4, it may not negate it until PHOLD#

is negated by PIIX4. PIIX4 implements the passive release mechanism by toggling

PHOLD# inactive for one PCICLK.

During Reset: High-Z After Reset: High During POS: High

PHLDA# I PCI HOLD ACKNOWLEDGE. An active low assertion indicates that PIIX4 has been

granted use of the PCI Bus. Once PHLDA# is asserted, it cannot be negated unless

PHOLD# is negated first.

SERR# I/O SYSTEM ERROR. SERR# can be pulsed active by any PCI device that detects a

system error condition. Upon sampling SERR# active, PIIX4 can be programmed to

generate a non-maskable interrupt (NMI) to the CPU.

During Reset: High-Z After Reset: High-Z During POS: High-Z

82371AB (PIIX4) E

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

Name Type Description

STOP# I/O STOP. STOP# indicates that PIIX4, as a Target, is requesting an initiator to stop the

current transaction. As an Initiator, STOP# causes PIIX4 to stop the current transaction.

STOP# is an output when PIIX4 is a Target and an input when PIIX4 is an Initiator.

STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until

driven by PIIX4 as a slave.

During Reset: High-Z After Reset: High-Z During POS: High-Z

TRDY# I/O TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data phase

of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is

completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY#

indicates that PIIX4, as a Target, has place valid data on AD[31:0]. During a write, it

indicates PIIX4, as a Target is prepared to latch data. TRDY# is an input to PIIX4 when

PIIX4 is the Initiator and an output when PIIX4 is a Target. TRDY# is

tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated until driven

by PIIX4 as a slave.

During Reset: High-Z After Reset: High-Z During POS: High-Z

NOTES:

All of the signals in the host interface are described in the Pentium Processor data sheet. The preceding table

highlights PIIX4 specific uses of these signals.

2.1.2. ISA BUS INTERFACE

Name Type Description

AEN O ADDRESS ENABLE. AEN is asserted during DMA cycles to prevent I/O slaves from

misinterpreting DMA cycles as valid I/O cycles. When negated, AEN indicates that an

I/O slave may respond to address and I/O commands. When asserted, AEN informs

I/O resources on the ISA bus that a DMA transfer is occurring. This signal is also

driven high during PIIX4 initiated refresh cycles.

During Reset: High-Z After Reset: Low During POS: Low

BALE O BUS ADDRESS LATCH ENABLE. BALE is asserted by PIIX4 to indicate that the

address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. The LA[23:17]

address lines are latched on the trailing edge of BALE. BALE remains asserted

throughout DMA and ISA master cycles.

During Reset: High-Z After Reset: Low During POS: Low

IOCHK#/

GPI0

I I/O CHANNEL CHECK. IOCHK# can be driven by any resource on the ISA bus.

When asserted, it indicates that a parity or an uncorrectable error has occurred for

a device or memory on the ISA bus. A NMI will be generated to the CPU if the NMI

generation is enabled. If the EIO bus is used, this signal becomes a general purpose

input.

E 82371AB (PIIX4)

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

Name Type Description

IOCHRDY I/O I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to indicate that

wait states are required to complete the cycle. This signal is normally high. IOCHRDY

is an input when PIIX4 owns the ISA Bus and the CPU or a PCI agent is accessing an

ISA slave, or during DMA transfers. IOCHRDY is output when an external ISA Bus

Master owns the ISA Bus and is accessing DRAM or a PIIX4 register. As a PIIX4

output, IOCHRDY is driven inactive (low) from the falling edge of the ISA commands.

After data is available for an ISA master read or PIIX4 latches the data for a write

cycle, IOCHRDY is asserted for 70 ns. After 70 ns, PIIX4 floats IOCHRDY. The 70 ns

includes both the drive time and the time it takes PIIX4 to float IOCHRDY. PIIX4 does

not drive this signal when an ISA Bus master is accessing an ISA Bus slave.

During Reset: High-Z After Reset: High-Z During POS: High-Z

IOCS16# I 16-BIT I/O CHIP SELECT. This signal is driven by I/O devices on the ISA Bus to

indicate support for 16-bit I/O bus cycles.

IOR# I/O I/O READ. IOR# is the command to an ISA I/O slave device that the slave may drive

data on to the ISA data bus (SD[15:0]). The I/O slave device must hold the data valid

until after IOR# is negated. IOR# is an output when PIIX4 owns the ISA Bus. IOR# is

an input when an external ISA master owns the ISA Bus.

During Reset: High-Z After Reset: High During POS: High

IOW# I/O I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may latch

data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns the ISA

Bus. IOW# is an input when an external ISA master owns the ISA Bus.

During Reset: High-Z After Reset: High During POS: High

LA[23:17]/

GPO[7:1]

I/O ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on the

ISA Bus up to 16 Mbytes. LA[23:17] are outputs when PIIX4 owns the ISA Bus. The

LA[23:17] lines become inputs whenever an ISA master owns the ISA Bus.

If the EIO bus is used, these signals become a general purpose output.

During Reset: High-Z After Reset: Undefined During POS: Last LA/GPO

MEMCS16# I/O MEMORY CHIP SELECT 16. MEMCS16# is a decode of LA[23:17] without any

qualification of the command signal lines. ISA slaves that are 16-bit memory devices

drive this signal low. PIIX4 ignores MEMCS16# during I/O access cycles and refresh

cycles. MEMCS16# is an input when PIIX4 owns the ISA Bus. PIIX4 drives this signal

low during ISA master to PCI memory cycles.

During Reset: High-Z After Reset: High-Z During POS: High-Z

MEMR# I/O MEMORY READ. MEMR# is the command to a memory slave that it may drive data

onto the ISA data bus. MEMR# is an output when PIIX4 is a master on the ISA Bus.

MEMR# is an input when an ISA master, other than PIIX4, owns the ISA Bus. This

signal is also driven by PIIX4 during refresh cycles. For DMA cycles, PIIX4, as a

master, asserts MEMR#.

During Reset: High-Z After Reset: High During POS: High

82371AB (PIIX4) E

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

PRELIMINARY

Name Type Description

MEMW# I/O MEMORY WRITE. MEMW# is the command to a memory slave that it may latch data

from the ISA data bus. MEMW# is an output when PIIX4 owns the ISA Bus. MEMW#

is an input when an ISA master, other than PIIX4, owns the ISA Bus. For DMA cycles,

PIIX4, as a master, asserts MEMW#.

During Reset: High-Z After Reset: High During POS: High

REFRESH# I/O REFRESH. As an output, REFRESH# is used by PIIX4 to indicate when a refresh

cycle is in progress. It should be used to enable the SA[7:0] address to the row

address inputs of all banks of dynamic memory on the ISA Bus. Thus, when MEMR#

is asserted, the entire expansion bus dynamic memory is refreshed. Memory slaves

must not drive any data onto the bus during refresh. As an output, this signal is driven

directly onto the ISA Bus. This signal is an output only when PIIX4 DMA refresh

controller is a master on the bus responding to an internally generated request for

refresh.

As an input, REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.

During Reset: High-Z After Reset: High During POS: High

RSTDRV O RESET DRIVE. PIIX4 asserts RSTDRV to reset devices that reside on the ISA/EIO

Bus. PIIX4 asserts this signal during a hard reset and during power-up. RSTDRV is

asserted during power-up and negated after PWROK is driven active. RSTDRV is

also driven active for a minimum of 1 ms if a hard reset has been programmed in the

RC register.

During Reset: High After Reset: Low During POS: Low

SA[19:0] I/O SYSTEM ADDRESS[19:0]. These bi-directional address lines define the selection

with the granularity of 1 byte within the 1-Megabyte section of memory defined by the

LA[23:17] address lines. The address lines SA[19:17] that are coincident with

LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles.

For I/O accesses, only SA[15:0] are used, and SA[19:16] are undefined. SA[19:0] are

outputs when PIIX4 owns the ISA Bus. SA[19:0] are inputs when an external ISA

Master owns the ISA Bus.

During Reset: High-Z After Reset: Undefined During POS: Last SA

SBHE# I/O SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a byte is

being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated

during refresh cycles. SBHE# is an output when PIIX4 owns the ISA Bus. SBHE# is

an input when an external ISA master owns the ISA Bus.

During Reset: High-Z After Reset: Undefined During POS: High

SD[15:0] I/O SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on the ISA

Bus. SD[15:8] correspond to the high order byte and SD[7:0] correspond to the low

order byte. SD[15:0] are undefined during refresh.

During Reset: High-Z After Reset: Undefined During POS: High-Z

SMEMR# O STANDARD MEMORY READ. PIIX4 asserts SMEMR# to request an ISA memory

slave to drive data onto the data lines. If the access is below the 1-Mbyte range

(00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or ISA master

cycles, PIIX4 asserts SMEMR#. SMEMR# is a delayed version of MEMR#.

During Reset: High-Z After Reset: High During POS: High

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