AR6002单芯片MAC/BB/Radio：2.4/5GHz嵌入式WLAN解决方案

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AR6002数据手册PDF文件概述了Atheros公司的一款高性能单芯片MAC/BB（媒体接入控制/基带）/射频解决方案，专为2.4 GHz和5 GHz嵌入式WLAN应用设计。这款产品是AR6001系列的升级版，旨在提供先进的性能和功能，同时具备紧凑的尺寸和低功耗特性，非常适合集成到便携式电子设备如手持设备中，以增强其无线连接能力。 AR6002集成了2.4 GHz IEEE 802.11g和5 GHz IEEE 802.11a标准的支持，这意味着它能够在两个主要的Wi-Fi频段上提供高速无线通信。这在移动设备和消费电子产品中非常关键，因为用户对于无缝的多频段连接有着很高的需求。该芯片支持两种常见的接口：SDIO 1.1和GSPI（通用串行总线接口），这两种接口允许AR6002与各种类型的主机系统轻松集成。SDIO接口常用于手机和平板电脑，而GSPI则为更广泛的设备提供了灵活性。 AR6002的设计目标是高度集成和前向兼容性，这意味着它能减少外部组件的需求，简化电路板设计，并且能够适应未来技术的发展。它的集成式架构有助于降低总体成本，提高产品的市场竞争力。此外，由于是"初步"版本的数据手册，可能还包含了预览性质的功能和技术细节，比如Atheros TurboMode，这是一种旨在优化无线性能的技术，以及Airis Cleaner at 5-GHz，可能指的是在5 GHz频段下的信号优化技术，以提供更清晰、稳定的无线信号。 AR6002作为一款关键的无线通信解决方案，它的特点包括强大的标准支持、多接口兼容性、低功耗和高度集成，使其成为构建现代便携设备无线功能的理想选择。随着技术的不断发展，AR6002的数据手册可能会包含更多创新的特性和优化，为无线网络的未来提供更多可能性。

10 • AR6002 MAC/BB/Radio for Embedded WLAN Applications Atheros Communications, Inc.

10 • April 2008 PRELIMINARY: ATHEROS CONFIDENTIAL

1.12.2 Sleep State Management

Sleep state minimizes power consumption

while saving system states. In deep sleep state,

all high speed clocks are gated off and the

external crystal is powered off. Light sleep is

similar to deep sleep, but the XTAL remains

running for faster WAKEUP. For the AR6002 to

enter sleep state, the MAC, SDIO/MBOX, and

CPU systems must be in sleep state.

When the embedded XTENSA CPU executes

the WAITI command, the SDIO/MBOX is idle

and the MAC system is in sleep state, the

AR6002 enters the system Sleep state. In sleep

state, the system gates all clock trees based on

REF_CLK with only the sleep clock logic

operating. The system remains in sleep state

until a WAKEUP event causes the system to

enter WAKEUP state, wait for the high

frequency clock source to stabilize, and finally

ungate all enabled clock trees. The CPU exits

the WAITI state only when an interrupt

arrives, which may result from the system

WAKEUP event.

1.13 System Clocking (RTC Block)

The AR6002 has an RTC block which controls

the clocks and power going to other internal

modules. Its inputs consist of sleep requests

from these modules and its outputs consists of

clock enable and power signals which are used

to gate the clocks going to these modules. The

RTC block also manages resets going to other

modules with the device. The AR6002’s

clocking is grouped into two types: high-speed

and low-speed.

1.13.1 High Speed Clocking

The crystal drives the primary clock source for

the internal PLL within the AR6002. REF_CLK

is the primary clock source for the analog and

digital systems. It is a high-frequency clock

sourced from either an external crystal or

oscillator source. It is the input to the RF

synthesizer for generating required frequencies

for proper 802.11 operation. An on-chip PLL

creates the appropriate clock frequency for

digital logic. When the AR6002 is in SLEEP

state, REF_CLK is not needed. To minimize

power consumption, the REF_CLK generator

shuts down during deep sleep. If an external

crystal is being used, the AR6002 disables the

on-chip oscillator driver. If REF_CLK is coming

from an external oscillator source, the AR6002

de-asserts its CLK_REQ signal and the external

clock source may shut down REF_CLK.

The PLL output is programmable but it will

usually run at one of only two frequencies: 320

MHz (during 802.11a mode) or 352 MHz

(during 802.11 b/g mode). This base clock is

divided into several clocks for the MAC and BB

modules. There are clocks running at 160 MHz,

80 MHz, and 40 MHz going to the MAC and BB

modules for 802.11a mode. (In 802.11g mode,

these are running at 176 MHz, 88 MHz, and 44

MHz.)

The SOC clock comes from a clock divider

module which divides the base clock by a

programmable value. By default, this value is

8. Hence in 802.11a mode (320 MHz base

clock), the default SOC frequency is 40 MHz

and in 802.11b/g mode (352 MHz base clock),

the SOC frequency is 44 MHz.

When the AR6002 exits SLEEP state, it enters

WAKEUP state and asserts CLK_REQ or

enables its internal crystal oscillator depending

on the clock configuration. The AR6002

remains in WAKEUP state for a programmable

duration that must cover clock settling time.

CLK_REQ remains asserted in WAKEUP and

ON states.

1.13.2 Low-Speed Clocking

The AR6002 has eliminated the need for a

second crystal thereby reducing system cost.

Instead, there is now a ring oscillator which

produces a clock that is nominally running at 2

MHz, but this can depending on process and

temperature.

The AR6002 has an internal calibration module

which produces a 32.768 KHz output with

minimal variation. For this, it uses the high-

speed crystal input as the golden clock.

Typically, this crystal input is only available

when the system is in the normal operating

state and is shut down during network sleep.

Hence the calibration module can adjust for

process and temperature variations only when

the system is in the normal operating state.

During network sleep, this module cannot

adjust for variations in the ring-oscillator

output.

In case the output from the calibration module

is not accurate enough, the AR6002 does have

the capability to use an external low-speed

clock source. This external clock source can be

used as the sleep clock instead of the

calibration module output. GPIO_8 in the

AR6002 can be used as the external clock

source pin.

Atheros Communications, Inc. AR6002 MAC/BB/Radio for Embedded WLAN Applications • 11

PRELIMINARY: ATHEROS CONFIDENTIAL April 2008 • 11

However, the external clock source need not

run at 32 KHz. It can be running at any similar

low frequency. The TSF and other low

frequency timers need to be programmed to

match this frequency.

In addition to providing the low-frequency

sleep clock for the AR6002, the 2 MHz ring

oscillator also runs the state machines and

counters inside the AR6002's Power Control

Module (PCM). The PCM controls all power

and isolation control signals for the entire chip.

1.13.3 Interface Clock

In addition to the clocking mentioned above,

there is another clock source for the AR6002.

This clock is referred to as the host clock (either

SDIO or GSPI). This clock is completely

independent from those mentioned above and

is driven by the external host to communicate

with the AR6002

This clock drives the interface logic as well as a

few registers which can be accessed by the

host. This allows this host to probe some

AR6002 information, including SDIO Common

I/O Area (CIA), when the AR6002 is in SLEEP

state.

1.13.4 Antenna Switching

For designs that use external front-end

components, the AR6002 provides the ability to

control those components and the internal

LNA with the antenna switch table. The switch

table (see Table 1-2) contains 10 entries, each 5

bits wide, and is indexed by:

■ The antenna selected by the MAC

■ The state of the transceiver (idle, receive, or

transmit)

■ Controls for Rx attenuation

When fast-receive antenna diversity is enabled,

the baseband will temporarily override the

antenna selected by the MAC once a packet has

been detected.

NOTE: Refer to AR6002 ART Reference Guide for more details on switching.

Table 1-2. Switch Table

Chip

State

Ant

Select Rx Atten Register Name

Idle — — BB_ANTENNA_CONTROL

Bluetooth

Active

— — BB_ANTENNA_CONTROL

Tx 1 — BB_SWITCH_TABLE1

Rx 1 No

Rx 1 Yes

Tx 2 — BB_SWITCH_TABLE2

Rx 2 No

Rx 2 Yes

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