QSFP+ 10Gbs 4X Transceiver SFF-8436 规范详解

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"SFF委员会发布的SFF-8436规范详细定义了QSFP+ 10 Gbps 4X可插拔收发器的电气、光学和机械特性。该文档旨在为系统制造商、系统集成商和驱动供应商提供通用标准，并计划取代INF-8438，增加了对10 Gbps数据速率的支持并更新了机械规格。此规范是SFF委员会内部工作文档，公开接受读者的评论和建议，以供未来修订时参考。" QSFP+（quad small form-factor pluggable plus）是一种高速光模块接口标准，用于数据中心和电信网络中的高密度光纤连接。SFF-8436规范是QSFP+ 10 Gbps 4X可插拔收发器的详细技术标准，由SFF委员会制定，该委员会是一个业界自发组织。这个规范的发布是为了确保不同供应商的QSFP+模块和直接连接电缆之间的互操作性。 1. **电气特性**：SFF-8436规范详细规定了收发器在10 Gbps数据速率下的电气性能。这包括信号完整性、电源电压、电流消耗、电磁兼容性（EMC）以及接口的电气接口标准，如LVDS（低压差分信号）等。 2. **光学特性**：在光学部分，规范涵盖了光源类型（例如，激光二极管或垂直腔面发射激光器）、光功率预算、光接收灵敏度、光学接口的反射和串扰控制，以及光通道的质量和稳定性要求。 3. **机械特性**：机械特性涉及到模块的物理尺寸、插拔接口、热插拔能力、散热设计、机械耐久性和环境适应性，确保模块能在各种温度、湿度和振动条件下稳定工作。 4. **兼容性与互操作性**：SFF-8436规范旨在确保不同制造商的QSFP+模块能无缝工作在相同的标准系统中，减少了系统集成的复杂性和成本。 5. **标准化过程**：作为一项公开的行业标准，SFF-8436允许公众审查和提出反馈，以不断改进和完善。这种开放的流程有助于推动技术进步，确保规范的全面性和前瞻性。 6. **支持成员**：SFF委员会的成员公司支持并遵循这个规范，这意味着这些公司在其产品开发中会按照SFF-8436的要求来设计和测试QSFP+模块，从而保证了市场的广泛接受和互操作性。 SFF-8436规范对于QSFP+ 10 Gbps 4X可插拔收发器的标准化和广泛应用起到了关键作用，促进了高速网络通信设备的快速发展和兼容性。随着技术的进步，这个规范也将不断更新，以适应更高的数据速率和新的应用场景。

Published SFF-8436 Rev 4.4

QSFP+ 10 Gbs 4X Pluggable Transceiver Page 14

should be isolated from the module’s circuit ground, GND, to provide the equipment

designer flexibility regarding connections between external electromagnetic interference

shields and circuit ground, GND, of the module.

Figure 2 QSFP+ Module Pad Layout

Published SFF-8436 Rev 4.4

QSFP+ 10 Gbs 4X Pluggable Transceiver Page 15

Table 3: Pin Function Definition (See Figure 10 for pad dimensions)

Logic Symbol Description Plug

Sequence

Notes

1 GND Ground 1 1

2 CML-I Tx2n Transmitter Inverted Data Input 3

3 CML-I Tx2p Transmitter Non-Inverted Data Input 3

4 GND Ground 1 1

5 CML-I Tx4n Transmitter Inverted Data Input 3

6 CML-I Tx4p Transmitter Non-Inverted Data Input 3

7 GND Ground 1 1

8 LVTTL-I

ModSelL

Module Select 3

9 LVTTL-I

ResetL Module Reset 3

10 Vcc Rx +3.3V Power Supply Receiver 2 2

11 LVCMOS-

I/O

SCL 2-wire serial interface clock 3

12 LVCMOS-

I/O

SDA 2-wire serial interface data 3

13 GND Ground 1 1

14 CML-O Rx3p Receiver Non-Inverted Data Output 3

15 CML-O Rx3n Receiver Inverted Data Output 3

16 GND Ground 1 1

17 CML-O Rx1p Receiver Non-Inverted Data Output 3

18 CML-O Rx1n Receiver Inverted Data Output 3

19 GND Ground 1 1

20 GND Ground 1 1

21 CML-O Rx2n Receiver Inverted Data Output 3

22 CML-O Rx2p Receiver Non-Inverted Data Output 3

23 GND Ground 1 1

24 CML-O Rx4n Receiver Inverted Data Output 3

25 CML-O Rx4p Receiver Non-Inverted Data Output 3

26 GND Ground 1 1

27 LVTTL-O

ModPrsL

Module Present 3

28 LVTTL-O

IntL Interrupt 3

29 Vcc Tx +3.3V Power supply transmitter 2 2

30 Vcc1 +3.3V Power supply 2 2

31 LVTTL-I

LPMode Low Power Mode 3

32 GND Ground 1 1

33 CML-I Tx3p Transmitter Non-Inverted Data Input 3

34 CML-I Tx3n Transmitter Inverted Data Input 3

35 GND Ground 1 1

36 CML-I Tx1p Transmitter Non-Inverted Data Input 3

37 CML-I Tx1n Transmitter Inverted Data Input 3

38 GND Ground 1 1

Note 1: GND is the symbol for signal and supply (power) common for the QSFP+

module. All are common within the QSFP+ module and all module voltages are

referenced to this potential unless otherwise noted. Connect these directly to the

host board signal-common ground plane.

Note 2:

Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and

shall be applied concurrently. Requirements defined for the host side of the Host

Edge Card Connector are listed in Table 6. Recommended host board power supply

filtering is shown in Figures 3 and 4. Vcc Rx Vcc1 and Vcc Tx may be internally

connected within the QSFP+ Module in any combination. The connector pins are each

rated for a maximum current of 500 mA.

Figure 3 shows an example of a complete QSFP+ host PCB schematic with connections to

SerDes and control ICs.

Published SFF-8436 Rev 4.4

QSFP+ 10 Gbs 4X Pluggable Transceiver Page 18

ModPrsL

IntL

4.1.1.1 ModSelL

The ModSelL is an input pin. When held low by the host, the module responds to 2-wire

serial communication commands. The ModSelL allows the use of multiple QSFP+ modules on a

single 2-wire interface bus. When the ModSelL is “High”, the module shall not respond to

or acknowledge any 2-wire interface communication from the host. ModSelL signal input

node must be biased to the “High” state in the module.

In order to avoid conflicts, the host system shall not attempt 2-wire interface

communications within the ModSelL de-assert time after any QSFP+ modules are deselected.

Similarly, the host must wait at least for the period of the ModSelL assert time before

communicating with the newly selected module. The assertion and de-asserting periods of

different modules may overlap as long as the above timing requirements are met.

4.1.1.2 ResetL

The ResetL pin must be pulled to Vcc in the QSFP+ module. A low level on the ResetL pin

for longer than the minimum pulse length (t_Reset_init) initiates a complete module

reset, returning all user module settings to their default state. Module Reset Assert

Time (t_init) starts on the rising edge after the low level on the ResetL pin is

released. During the execution of a reset (t_init) the host shall disregard all status

bits until the module indicates a completion of the reset interrupt. The module indicates

this by asserting “low” an IntL signal with the Data_Not_Ready bit negated. Note that on

power up (including hot insertion) the module should post this completion of reset

interrupt without requiring a reset.

4.1.1.3 LPMode

The LPMode pin shall be pulled up to Vcc in the QSFP+ module. This function is affected

by the LPMode pin and the combination of the Power_over-ride and Power_set software

control bits (Address A0h, byte 93 bits 0,1).

The module has two modes a low power mode and a high power mode. The high power mode

operates in one of the four power classes.

When the module is in a low power mode it has a maximum power consumption of 1.5W. This

protects hosts that are not capable of cooling higher power modules, should such modules

be accidentally inserted.

The modules 2-wire serial interface and all laser safety functions must be fully

operational in this low power mode. The module shall still support the completion of

reset interrupt in this low power mode.

If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate a power

consumption greater than 1.5W and the module is in low power mode it must reduce its

power consumption to less than 1.5W while still maintaining the functionality above. The

exact method of accomplishing low power is not specified, however it is likely that

either the Tx or Rx or both will not be operational in this state.

If the Extended Identifier bits (Page 00h, byte 129 bits 6-7) indicate that its power

consumption is less than 1.5W then the module shall be fully functional independent of

whether it is in low power or high power mode.

The Module should be in low power mode if the LPMode pin is in the high state, or if the

Power_ override bit is in the high state and the Power_set bit is also high. The

module should be in high power mode if the LPMode pin is in the low state, or the

Power_override bit is high and the Power_set bit is low. Note that the default state

for the Power_override bit is low.

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