PCI Express M.2 规范 Rev5.0：下一代高速接口标准

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"PCI Express M.2 规范第5.0版，版本1.0，发布于2023年4月29日" PCI Express（PCIe）M.2是现代计算机中广泛使用的高速接口标准，用于连接存储设备如固态硬盘（SSD）和其他扩展卡。此规范的第5.0版代表着技术的重大升级，提供了更高的数据传输速率和增强的系统性能。 PCIe M.2接口基于PCI Express总线协议，它允许设备之间以低延迟、高带宽的方式通信。在第5.0版中，该接口的数据传输速度显著提升，支持每个通道双向最高可达32 GT/s（吉比特每秒），比之前的4.0版本翻了一倍。这使得存储设备的读写速度可以达到数千兆字节每秒，极大地提升了存储性能。规范还包括对不同尺寸和形状因子的支持，以适应各种应用场合。例如，M.2接口有多种键位定义（如B key、M key、NB key等），它们决定了插槽能支持的设备类型和PCIe通道数量。B key通常用于SATA或USB等较慢的接口，而M key则支持全速PCIe连接。此外，还有不同长度的模块，如22mm、30mm、42mm等，适应不同的空间需求。 PCI-SIG（Peripheral Component Interconnect Special Interest Group）是负责制定和维护PCI标准的组织。在本规范中，他们明确指出，尽管尽力确保文档的准确性，但不保证文档内信息无误，也不承担任何错误导致的责任，并且不会承诺更新文档中的信息。获取最新修订版的规范应直接联系PCI-SIG办公室。对于技术问题或PCI-SIG会员相关事宜，可以通过提供的电子邮件地址和电话联系其 Membership Services 和 Technical Support 部门。同时，PCI-SIG强调，此规范的提供不附带任何保修，包括但不限于适销性、非侵权、适合特定目的的任何明示或暗示保修。使用此规范中的信息可能涉及侵犯第三方的知识产权，对此PCI-SIG不承担责任，也不提供任何形式的默示许可。 PCI Express M.2 规范第5.0版是当前计算机硬件领域的重要进步，为高性能存储和其他扩展设备提供了更强大的连接基础。随着技术的不断发展，未来我们有望看到更多利用此规范优势的产品和服务。

PCI Express M.2 Specification 
April 29, 2023 
PCI Express M.2 Specification  |  16 
Revision 5.0, Version 1.0 
Figure 2-80.  H2.5-S4- Stack-up Top Mount Single-sided Add-in Card for 1.75 Maximum  
Top-side Component Height and with Higher Clearance above Motherboard .............. 102 
Figure 2-81.  H2.5-S5- Stack-up Top Mount Single-sided Add-in Card for 2.00 Maximum  
Top-side Component Height and with Higher Clearance above Motherboard .............. 102 
Figure 2-82.  H2.8-D4 – Stack-up Top Mount Double-sided Add-in Card for 1.5 Maximum  
Top-side Component Height with 0.7 Maximum Bottom-side Component Height ......... 103 
Figure 2-83.  H3.2-D1 – Stack-up Top Mount Double-sided Add-in Card for 1.20 Maximum  
Top-side Component Height ....................................................................................... 103 
Figure 2-84.  H3.2-D2 – Stack-up Top Mount Double-sided Add-in Card for 1.35 Maximum  
Top-side Component Height ....................................................................................... 104 
Figure 2-85.  H3.2-D3 – Stack-up Top Mount Double-sided Add-in Card for 1.5 Maximum  
Top-side Component Height ....................................................................................... 104 
Figure 2-86.  H4.2-D5 – Stack-up Top Mount Double-sided Add-in Card for 1.5 Maximum  
Top-side Component Height with  1.5 Maximum Bottom-side Component Height ........ 104 
Figure 2-87.  H4.2-D8-P Stack-up Top Mount Double-sided Add-in Card for 3.2mm +0 / -0.5  
Top-side dimension and 1.5 Maximum Bottom-side Component Height ...................... 105 
Figure 2-88.  Example of Top Mount Motherboard Land Pattern - Key B Shown .............................. 105 
Figure 2-89.  Mid-mount (In-line) Connector Dimensions ................................................................. 107 
Figure 2-90.  Mid-mount (In-line) System Length ............................................................................. 108 
Figure 2-91.  Stack-up Mid-mount (In-line) Single-sided (S1) Add-in Card for 1.2 Maximum  
Component Height ...................................................................................................... 109 
Figure 2-92.  Stack-up Mid-mount (In-line) Single-sided (S2) Add-in Card for 1.35 Maximum 
Component Height ...................................................................................................... 109 
Figure 2-93.  Stack-up Mid-mount (In-line) Single-sided (S3) Add-in Card for 1.5 Maximum  
Component Height ...................................................................................................... 109 
Figure 2-94.  Stack-up Mid-mount (In-line) Double-sided (D1) Add-in Card for 1.2 Maximum  
Top-side Component Height ....................................................................................... 110 
Figure 2-95.  Stack-up Mid-mount (In-line) Double-sided (D2) Add-in Card for 1.35 Maximum  
Top-side Component Height ....................................................................................... 110 
Figure 2-96.  Stack-up Mid-mount (In-line) Double-sided (D3) Add-in Card for 1.5 Maximum  
Top-side Component Height ....................................................................................... 111 
Figure 2-97.  Stack-up Mid-mount (In-line) Double-sided (D4) Add-in Card for 1.5 Maximum  
Top-side Component Height ....................................................................................... 111 
Figure 2-98.  Stack-up Mid-mount (In-line) Double-sided (D5) Add-in Card for 1.5 Maximum  
Top-side and Bottom-side Component Height ............................................................. 111 
Figure 2-99.  Example of Mid-mount Motherboard Land Pattern Diagram – Key B Shown................ 112 
Figure 2-100.  Connector Key............................................................................................................ 113 
Figure 2-101.  M.2 Connector Keying Diagram .................................................................................. 114 
Figure 2-102.  Dual Add-in Card Key Scheme Example ..................................................................... 115 
Figure 2-103.  Mid-mount Add-in Card Mounting Interface ................................................................. 116 
Figure 2-104.  Single-sided Top Mount Solder-down Stand-off .......................................................... 117 
Figure 2-105.  Elevated Single-sided Top Mount Solder Stand-off ..................................................... 117 
Figure 2-106.  Low Profile Double-sided Top Mount Solder-down Stand-off ....................................... 118 
Figure 2-107.  Double-sided Top Mount Solder-down Stand-off ......................................................... 118 
Figure 2-108.   Elevated Double-sided Top Mount Solder-down Stand-off........................................... 118 
Figure 2-109.   Flat Stand-off .............................................................................................................. 119 
Figure 2-110.  Shouldered Stand-off .................................................................................................. 120 
Figure 2-111.  Screw Guidelines........................................................................................................ 120 

PCI Express M.2 Specification 
April 29, 2023 
PCI Express M.2 Specification  |  17 
Revision 5.0, Version 1.0 
Figure 2-112.  Wafer-head Style M3 Screw ....................................................................................... 121 
Figure 2-113.  M3 Screw with Tapered Shaft ..................................................................................... 121 
Figure 2-114.  Wafer-head Style M2 Screw ....................................................................................... 122 
Figure 2-115.  Flat-head Style M3 Screw ........................................................................................... 122 
Figure 3-1.  CLKREQ# Clock Control Timings ............................................................................... 134 
Figure 3-2.  Power-up Timing Sequence for an Adapter Powered from System Power Rail ............ 136 
Figure 3-3.  SDIO Reset Sequence ............................................................................................... 139 
Figure 3-4.  SDIO Power-up Sequence .......................................................................................... 139 
Figure 3-5.  UART Frame Format .................................................................................................. 140 
Figure 3-6.  Typical PCM Transaction Timing Diagram .................................................................. 141 
Figure 3-7.   Supplemental NFC Signal Connection Example .......................................................... 143 
Figure 3-8.  Typical LED Connection Example in Platform/System ................................................. 144 
Figure 3-9.  Type 2226 SDIO Based Module-side Pinout ............................................................... 152 
Figure 3-10.  Type 1216 SDIO Based Module-side Pinout ............................................................... 153 
Figure 3-11.  Type 3026 DisplayPort Pinouts Extension Over an SDIO Based Module-side Pinout .. 154 
Figure 3-12.  Power-up Timing Sequence for a WWAN Specific Adapter Powered by a  
Direct V
BAT
 Connection ............................................................................................... 159 
Figure 3-13.  Typical SIM Detect Circuit Implementation .................................................................. 162 
Figure 3-14.  Example of a Connection of the GNSS Signals in a Platform Using M.2 Adapter ......... 165 
Figure 3-15.  WAKE_ON_WWAN# Signal ....................................................................................... 166 
Figure 3-16.  Power Loss Sequencing Behavior for Socket 2 ........................................................... 171 
Figure 3-17.  Power Loss Sequencing Behavior for Socket 3 ........................................................... 186 
Figure 3-18.  Type 1620 BGA Module-side Ballmap (Top View) ....................................................... 200 
Figure 3-19.  Type 1620 BGA Module-side Ballmap Surrounded by  Type 2024, Type 2228, 
 and Type 2828 Module-side Ballmaps (Top View)...................................................... 201 
Figure 3-20.  Type 1113 BGA Module-side Ballmap (Top View) ....................................................... 202 
Figure 4-1.  Power-on Sequencing Examples ................................................................................ 207 
Figure 4-2.  Power-off Sequencing Examples ................................................................................ 208 
Figure 4-3.  8.0 GT/s M.2 Add-in Card Transmitter Path Compliance Eye Diagram ........................ 211 
Figure 4-4.  8.0 GT/s System Board Transmitter Path Composite Compliance Eye Diagram .......... 214 
Figure 4-5.  16.0 GT/s System Board Transmitter Path Composite Compliance Eye Diagram ........ 219 
Figure 4-6.  TX Equalization Based on AC Fit Method ................................................................... 226 
Figure 5-1.  Type 2226 LGA Pinout Using SDIO Based Socket 1 Pinout on Platform ..................... 248 
Figure 5-2.  Type 1216 LGA Pinout Using SDIO Based Socket 1 Pinout on Platform ..................... 249 
Figure 5-3.  Type 3026 LGA Pinout Using SDIO Based Socket 1 and DisplayPort  
Based Socket 1 Pinout on Platform ............................................................................. 250 
Figure 5-4.  Type 1620 BGA Pinout on Platform (Top View)........................................................... 251 
Figure 5-5.  Type 1620 BGA Module-side Pinout Surrounded by Type 2024, Type 2228,  
and Type 2828 Platform-side Pinout (Top View) ......................................................... 252 
Figure 5-6.  Type 1113 BGA Socket Map on Platform (Top View) .................................................. 253 
Figure 6-1.  UART and PCM Signal Direction and Signal Name Changes ...................................... 255 
Figure 6-2.  PCIe Signal Direction and Signal Name Changes ....................................................... 256 
Figure 6-3.  COEX_TXD and COEX_RXD Signal Direction ............................................................ 256 
Figure 6-4.  Suggested Motherboard and Add-in Card Signals and Ground Pad Layout Guideline . 258 
Figure 6-5.  Suggested Ground Void for Add-in Card Simulation .................................................... 259 
Figure 6-6.  Suggest Ground Void for Main Board .......................................................................... 259 

PCI Express M.2 Specification 
April 29, 2023 
PCI Express M.2 Specification  |  18 
Revision 5.0, Version 1.0 
Figure 6-7.  Top Mount Add-in Card Test Fixture PCB Layout ........................................................ 260 
Figure 6-8.  Top Mount Motherboard Test Fixture PCB .................................................................. 261 
Figure 6-9.  Top Mount Connector Test Fixture .............................................................................. 262 
Figure 6-10.  Mid-mount Connector Test Fixture .............................................................................. 263 
Figure 6-11.  Mid-mount Add-in Card Test Fixture PCB Layout ........................................................ 263 
Figure 6-12.  Mid-mount Motherboard Test Fixture PCB .................................................................. 264 
Figure 6-13.  Detail of Top-side SMA End Launch Connector Pad ................................................... 264 
Figure 6-14.  Ground Void on Backside ........................................................................................... 265 
Figure 6-15.  Detail of Mid-mount Vias on Top-side Motherboard ..................................................... 266 
Figure 6-16.  Detail of Ground Void on Mid-mount Bottom Side Motherboard ................................... 266 
Figure 6-17.  Differential Insertion Loss Limits for 16.0 GT/s Operation ............................................ 268 
Figure 6-18.  Differential Return Loss Limits for 16.0 GT/s Operation ............................................... 269 
Figure 6-19.  Differential Near End and Far End Crosstalk Limits for 16.0 GT/s Operation ............... 269 
Figure 6-20.  Differential Insertion Loss Limits for 32.0 GT/s Operation ............................................ 272 
Figure 6-21.  Differential Return Loss Limits for 32.0 GT/s Operation ............................................... 273 
Figure 6-22.  Differential Near End Crosstalk Limits for 32.0 GT/s Operation ................................... 273 
Figure 6-23.  Differential Far End Crosstalk Limits for 32.0 GT/s Operation ...................................... 274 
Figure 6-24.  Near End Crosstalk Victim and Aggressors for the PCIe Based Pinout  
(Socket 2 & 3)............................................................................................................. 275 
Figure 6-25.  Far End Crosstalk Victim and Aggressors for the PCIe Based Pinout .......................... 275 
Figure 6-26.  Suggested Add-in Card Signals and Ground Pad Layout Guideline  
(Top View and Side Cross-section View) .................................................................... 278 
Figure 6-27.  Suggested Ground Void for Add-in Card Simulation .................................................... 279 
Figure 6-28.  Suggested Ground Void for Add-in Card ..................................................................... 279 
Figure 6-29.  Suggested Ground Void for Main Board ...................................................................... 279 
Figure 6-30.  Top Mount Add-in Card Test Fixture PCB Layout ........................................................ 280 
Figure 6-31.  Top Mount Motherboard Test Fixture PCB .................................................................. 281 
Figure 6-32.  VSWR Test Setup for Receptacle RF Connector ........................................................ 282 
Figure 6-33.  Contact Resistance Measurement Definitions ............................................................. 282 
Figure 6-34.  Prepared Wires .......................................................................................................... 283 
Figure 6-35.  Prepared Wire with Plug ............................................................................................. 283 
Figure 6-36.  Example View of Notebook Motherboard .................................................................... 293 
Figure 6-37.  Example View of Edge Vents ...................................................................................... 293 
Figure 6-38.  Example View of Bottom Vents (vent opening where inside boards are  
visible through the opening) ........................................................................................ 293 
Figure 6-39.  Example View of Region Over Adapters ..................................................................... 294 
Figure 6-40.  Example View of Hot Spot Over Adapters ................................................................... 294 
Figure 6-41.  Example View of Motherboard for Thin Platform Notebook with Fan............................ 297 
Figure 6-42.  Thin Platform Notebook Layout with Vents and Key Components ............................... 298 
Figure 6-43.  Example View of Region and Hot Spots Over Adapters .............................................. 299 
Figure 6-44.  Example View of Region and Hot Spots Under Adapters ............................................ 299 
Figure 6-45.  Example View of Tablet Motherboard ......................................................................... 303 
Figure 6-46.  Example View of System Layout, Including Table ....................................................... 304 
Figure 6-47.  Example View of Display Surface Temperature with WWAN Use Case Estimate II...... 305 
Figure 6-48.  AC Coupling Capacitor Location – PCIe and USB3.1 Pluggable  
Add-in Card Example.................................................................................................. 310 

PCI Express M.2 Specification 
April 29, 2023 
PCI Express M.2 Specification  |  20 
Revision 5.0, Version 1.0 
List of Tables 
Table 2-1.  Optional Adapter Configurations ........................................................................................ 35 
Table 2-2.  General Tolerance............................................................................................................. 36 
Table 2-3.  Key Location/Pin Block Dimensions for Keys A to F ........................................................... 61 
Table 2-4.  Key Location/Pin Block Dimensions for Keys G to M .......................................................... 61 
Table 2-5.  RF Connector Physical Characteristics .............................................................................. 86 
Table 2-6.  RF Connector Mechanical Requirements........................................................................... 86 
Table 2-7.  RF Connector Electrical Requirements .............................................................................. 87 
Table 2-8.  RF Connector Environmental Requirements ...................................................................... 87 
Table 2-9.  Recommended Antenna Function Allocation Table ............................................................ 88 
Table 2-10.  Connector/Adapter Height Supported Matrix ...................................................................... 91 
Table 2-11.  Connector Physical Requirements ..................................................................................... 92 
Table 2-12.  Connector Environmental Requirements............................................................................ 93 
Table 2-13.  Connector Electrical Requirements .................................................................................... 93 
Table 2-14.  M.2 and M.2-1A Connector and Card Insertion Capability Matrix ..................................... 106 
Table 2-15.  Stand-off Height Descriptor Table .................................................................................... 119 
Table 3-1.  Socket 1 System Interface Signals and Voltage Table ..................................................... 126 
Table 3-2.  M.2 Clocking Architecture Requirements ......................................................................... 131 
Table 3-3.  M.2 Common Clock Architecture Details .......................................................................... 132 
Table 3-4.  Maximum Allowed Reference Clock RMS Rj Phase Jitter ................................................ 132 
Table 3-5.  Power-up CLKREQ# Timings .......................................................................................... 135 
Table 3-6.  Power-up and Additional PERST Timing Variables .......................................................... 136 
Table 3-7.  DP_MLDIR Pin Termination ............................................................................................ 138 
Table 3-8.  SDIO Reset and Power-up Timing ................................................................................... 139 
Table 3-9.  Simple Indicator Protocol for LED States ......................................................................... 144 
Table 3-10.  Radio Operational States................................................................................................. 146 
Table 3-11.  Wireless Disable Pin Mode and Function Assignment ...................................................... 146 
Table 3-12.  SDIO Based Add-in Card Pinouts (Key E) ....................................................................... 149 
Table 3-13.  DisplayPort Based Add-in Card Pinouts (Key A) .............................................................. 150 
Table 3-14.  Socket 1 Add-in Card Pinouts (Key A-E) .......................................................................... 151 
Table 3-15.  Socket 2 System Interface Signal Table........................................................................... 155 
Table 3-16.  GPIO Pin Function Assignment per Port Configuration .................................................... 163 
Table 3-17.  Audio Pin Mode and Function Assignment ....................................................................... 166 
Table 3-18.  Antenna Control Pin Mode and Function Assignment ...................................................... 167 
Table 3-19.  Socket 2 Add-in Card Configuration ................................................................................. 168 
Table 3-20.  Socket 2 Key B SSIC-based WWAN Adapter Pinout ........................................................ 173 