TI TPS65982：USB-C和PD控制器，3A电源开关

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TI-TPS65982是一款高性能的USB Type-C和USB Power Delivery (USB PD)控制器，它集成了多种关键功能，旨在简化并优化USB Type-C接口的实现。该器件具有以下主要特点： 1. **USB PD控制器**：作为核心组件，TPS65982支持多种工作模式，包括供电主机、受电设备以及供电-受电模式，允许灵活的应用场景配置。它具备双相标记编码/解码（BMC）能力，确保数据传输的正确识别。 2. **物理层(PHY)协议支持**：该控制器负责处理USB Type-C的物理层通信，包括PHY协议，保证数据传输的稳定性和兼容性。 3. **策略引擎**：通过策略引擎，TPS65982可以智能地管理电源供应，根据应用需求自动调整配置，同时支持引导控制和主机控制两种工作模式。 4. **USB Type-C规范兼容**：TPS65982严格遵循USB Type-C标准，能够检测USB电缆的连接状态，识别电缆的方向和角色，同时精确分配CC和VCONN引脚，以满足不同电压和电流需求。 5. **端口电源开关**：该控制器配备有多个开关功能： - 5V/3A的VBUS开关，用于在Type-C电源和其他电源之间切换。 - 5V至20V双向开关，可在USB PD电源和Type-C电源之间切换，支持更大的电压范围。 - 5V/600mA的VCONN开关，确保VCONN线路上的适当电流供应。 6. **电压和电流控制**：支持为5V USB Type-C提供默认值、1.5A或3A的电流，以适应不同设备的需求。 7. **版权和文档更新**：本文档提供了TI-TPS65982中文版本的信息，但用户应参考www.ti.com的官方英文版以获取最新的技术规格和更新，因为英文资料始终是优先且最准确的来源。 TPS65982是一款高效能的Type-C控制器，为USB Type-C设备设计者提供了全面的电源管理和连接解决方案，适用于需要兼容USB PD和多种电源配置的应用场景。在实际设计时，务必查阅最新英文数据手册以确保设计的精确性和可靠性。

TPS65982

ZHCSDS8D –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

USB-PD TX Driver Voltage Adjustment Parameter (continued)

Recommended operating conditions; T

= –10 to 85°C unless otherwise noted

(1)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

VTXP10 TX transmit peak voltage 1.045 1.1 1.155 V

VTXP11 TX transmit peak voltage 1.021 1.075 1.128 V

VTXP12 TX transmit peak voltage 0.998 1.05 1.102 V

VTXP13 TX transmit peak voltage 0.974 1.025 1.076 V

VTXP14 TX transmit peak voltage 0.95 1 1.05 V

VTXP15 TX transmit peak voltage 0.903 0.95 0.997 V

(1) Maximum capacitance on VBUS when configured as a source must not exceed 12 µF.

(2) Settings selected automatically by application code for the current limit needed in the application.

7.11 Port Power Switch Characteristics

Recommended operating conditions; T

= –10 to 85°C unless otherwise noted

PARAMETER TEST CONDITIONS

(1)

MIN TYP MAX UNIT

RPPCC PP_CABLE to C_CCn power switch resistance 312 mΩ

RPP5V PP_5V0 to VBUS power switch resistance 50 60 mΩ

RPPHV PP_HV to VBUS power switch resistance 95 135 mΩ

IHVACT

Active quiescent current from PP_HV pin,

EN_HV = 1

IHVSD

Shutdown quiescent current from PP_HV pin,

EN_HV = 0

100

μA

IHVEXTACT

Active quiescent current from SENSEP pin,

EN_HV = 1

Configured as source 1

Active quiescent current from VBUS pin,

EN_HV = 1

Configured as sink 3.5

IHVEXTSD

Shutdown quiescent current from SENSEP pin,

EN_HV = 0

μA

IPP5VACT Active quiescent current from PP_5V0 1 mA

IPP5VSD Shutdown quiescent current from PP_5V0 100 μA

ILIMHV

(2)

PP_HV current limit, setting 0 1.007 1.118 1.330 A

PP_HV current limit, setting 1 1.258 1.398 1.638 A

PP_HV current limit, setting 2 1.51 1.678 1.945 A

PP_HV current limit, setting 3 1.761 1.957 2.153 A

PP_HV current limit, setting 4 2.013 2.237 2.46 A

PP_HV current limit, setting 5 2.265 2.516 2.768 A

PP_HV current limit, setting 6 2.516 2.796 3.076 A

PP_HV current limit, setting 7 2.768 3.076 3.383 A

PP_HV current limit, setting 8 3.02 3.355 3.691 A

PP_HV current limit, setting 9 3.271 3.635 3.998 A

PP_HV current limit, setting 10 3.523 3.914 4.306 A

PP_HV current limit, setting 11 3.775 4.194 4.613 A

PP_HV current limit, setting 12 4.026 4.474 4.921 A

PP_HV current limit, setting 13 4.278 4.753 5.228 A

PP_HV current limit, setting 14 4.529 5.033 5.536 A

PP_HV current limit, setting 15 5.033 5.592 6.151 A

TPS65982

www.ti.com.cn

ZHCSDS8D –MARCH 2015–REVISED JUNE 2019

Port Power Switch Characteristics (continued)

Recommended operating conditions; T

= –10 to 85°C unless otherwise noted

PARAMETER TEST CONDITIONS

(1)

MIN TYP MAX UNIT

(3) Specified for a 10-mΩ RSENSE resistor and 10-m Ω RSENSE application code setting. Values will scale with a different RSENSE

resistance and application code setting.

(4) The current sense in the ADC will not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV because of the reverse

blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid.

ILIMHVEXT

(3)(2)

PP_EXT current limit, setting 0 0.986 1.12 1.254 A

PP_EXT current limit, setting 1 1.231 1.399 1.567 A

PP_EXT current limit, setting 2 1.477 1.678 1.879 A

PP_EXT current limit, setting 3 1.761 1.957 2.153 A

PP_EXT current limit, setting 4 2.012 2.236 2.46 A

PP_EXT current limit, setting 5 2.263 2.515 2.767 A

PP_EXT current limit, setting 6 2.514 2.794 3.074 A

PP_EXT current limit, setting 7 2.765 3.073 3.381 A

PP_EXT current limit, setting 8 3.016 3.352 3.688 A

PP_EXT current limit, setting 9 3.267 3.631 3.995 A

PP_EXT current limit, setting 10 3.519 3.91 4.301 A

PP_EXT current limit, setting 11 3.77 4.189 4.608 A

PP_EXT current limit, setting 12 4.021 4.468 4.915 A

PP_EXT current limit, setting 13 4.272 4.747 5.222 A

PP_EXT current limit, setting 14 4.523 5.026 5.529 A

PP_EXT current limit, setting 15 5.025 5.584 6.143 A

ILIMPP5V

(2)

PP_5V0 current limit, setting 0 1.006 1.118 1.330 A

PP_5V0 current limit, setting 1 1.132 1.258 1.484 A

PP_5V0 current limit, setting 2 1.258 1.398 1.638 A

PP_5V0 current limit, setting 3 1.384 1.538 1.691 A

PP_5V0 current limit, setting 4 1.51 1.677 1.845 A

PP_5V0 current limit, setting 5 1.636 1.817 1.999 A

PP_5V0 current limit, setting 6 1.761 1.957 2.153 A

PP_5V0 current limit, setting 7 1.887 2.097 2.307 A

PP_5V0 current limit, setting 8 2.013 2.237 2.46 A

PP_5V0 current limit, setting 9 2.139 2.376 2.614 A

PP_5V0 current limit, setting 10 2.265 2.516 2.768 A

PP_5V0 current limit, setting 11 2.39 2.656 2.922 A

PP_5V0 current limit, setting 12 2.516 2.796 3.075 A

PP_5V0 current limit, setting 13 2.642 2.936 3.229 A

PP_5V0 current limit, setting 14 2.768 3.075 3.383 A

PP_5V0 current limit, setting 15 3.019 3.355 3.69 A

ILIMPPCC

PP_CABLE current limit (highest setting) 0.6 0.75 0.9 A

PP_CABLE current limit (lowest setting) 0.35 0.45 0.55 A

IHV_ACC

(4)

PP_HV current sense accuracy

I = 100 mA Reverse current

blocking disabled

3.25 5 6.75

A/V

I = 200 mA 4 5 6 A/V

I = 500 mA 4.4 5 5.6 A/V

I ≥ 1 A 4.5 5 5.5 A/V

IHVEXT_ACC

PP_EXT current sense accuracy (excluding

RSENSE accuracy)

I = 100 mA , RSENSE = 10 mΩ

Reverse current blocking disabled

3.5 5 6.5

A/V

I = 200 mA, RSENSE = 10 mΩ 4 5 6 A/V

I = 500 mA, RSENSE = 10 mΩ 4.4 5 5.6 A/V

I ≥ 1 A, RSENSE = 10 mΩ 4.5 5 5.5 A/V

TPS65982

ZHCSDS8D –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

Port Power Switch Characteristics (continued)

Recommended operating conditions; T

= –10 to 85°C unless otherwise noted

PARAMETER TEST CONDITIONS

(1)

MIN TYP MAX UNIT

(5) Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ω to provide adequate response time to short circuit

events.

IPP5V_ACC

(4)

PP_5V0 current sense accuracy

I = 100 mA Reverse current

blocking disabled

1.95 3 4.05

A/V

I = 200 mA 2.4 3 3.6 A/V

I = 500 mA 2.64 3 3.36 A/V

I ≥ 1 A 2.7 3 3.3 A/V

IPPCBL_ACC PP_CABLE current sense accuracy

I = 100 mA 1 A/V

I = 200 mA 1 A/V

I = 500 mA 1 A/V

IGATEEXT

(5)

External Gate Drive Current on HV_GATE1

and HV_GATE2

4 5 6

μA

VGSEXT VGS voltage driving external FETs 4.5 7.5 V

TON_HV

PP_HV path turn on time from enable to VBUS

= 95% of PP_HV voltage

Configured as a source or as a

sink with soft start disabled.

PP_HV = 20 V, CVBUS = 10 μF,

ILOAD = 100 mA

TON_5V

PP_5V0 path turn on time from enable to

VBUS = 95% of PP_5V0 voltage

Configured as a source or as a

sink with soft start disabled.

PP_5V0 = 5 V, CVBUS = 10 μF,

ILOAD = 100 mA

2.5

TON_CC

PP_CABLE path turn on time from enable to

C_CCn = 95% of the PP_CABLE voltage

PP_CABLE = 5 V, C_CCn = 500

nF, ILOAD = 100 mA

ISS Soft start charging current 5.5 7 8.5 μA

RSS_DIS Soft start discharge resistance 0.6 1 1.4 kΩ

VTHSS Soft start complete threshold 1.35 1.5 1.65 V

TSSDONE Soft start complete time CSS = 220 nF 31.9 46.2 60.5 ms

VREVPHV

Reverse current blocking voltage threshold for

PP_HV switch

2 6 10

VREVPEXT

Reverse Current Blocking voltage Threshold for

PP_EXT external switches

2 6 10

VREV5V0

Reverse current blocking voltage threshold for

PP_5V0 switches

2 6 10

VHVDISPD

Voltage threshold above VIN at which the

pulldown RHVDISPD on VBUS will disable

during a transition from PHV to 5V0

45 200 250

VSAFE0V

Voltage that is a safe 0 V per USB-PD

Specifications

0 0.8

TSAFE0V Voltage transition time to VSAFE0V 650 ms

VSO_HV

Voltage on PP_HV or PP_HVEXT above which

the PP_HV or PP_EXT to PP_5V0 transition on

VBUS will meet transition requirements

9.9

SRPOS

Maximum slew rate for positive voltage

transitions

0.03

V/μs

SRNEG

Maximum slew rate for negative voltage

transitions

–0.03

V/μs

TSTABLE

EN to stable time for both positive and negative

voltage transitions

275

VSRCVALID

Supply output tolerance beyond VSRCNEW

during time TSTABLE

–0.5 0.5

VSRCNEW Supply output tolerance –5 5 %

TPS65982

www.ti.com.cn

ZHCSDS8D –MARCH 2015–REVISED JUNE 2019

(1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum

difference between the two switches in a pair. ROND does not add to RON.

7.12 Port Data Multiplexer Switching Characteristics

Recommended operating conditions; T

= –10 to 85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SWD MULTIPLEXER PATH

(1)

SWD_RON_U

On resistance of SWD_DATA/CLK to

C_USB_TP/TN/BP/BN

= 3.3 V, I

= 20 mA 35 55

= 1 V, I

= 20 mA 30 46

SWD_ROND_U

On resistance difference between P and N paths of

SWD_DATA/CLK to C_USB_ TP/TN/BP/BN

= 1 V to 3.3 V, I

= 20 mA –2.5 2.5 Ω

SWD_RON_S On resistance of SWD_DATA/CLK to C_SBU1/2

= 3.3 V, I

= 20 mA 26 42

= = 1 V, I

= 20 mA 24 37

SWD_ROND_S

On resistance difference between P and N paths of

SWD_DATA/CLK to C_SBU1/2

= 1V to 3.3 V, I

= 20 mA –1.5 1.5 Ω

SWD_TON Switch on time from enable of SWD path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

SWD_TOFF Switch off time from disable of SWD path

Time from disable bit at charge

pump steady state

500 ns

SWD_BW 3 dB bandwidth of SWD path C

= 10 pF 200 MHz

DEBUG1/2 MULTIPLEXER PATH

(1)

DB1_RON_U On resistance DEBUG1/2 to C_USB_TP/TN/BP/BN

= 3.3 V, I

= 20 mA 14 26

= 1 V, I

= 20 mA 10 17

DB1_ROND_U

On resistance difference between P and N paths of

DEBUG1/2 to C_USB_TP/TN/BP/BN

= 1 V to 3.3 V, I

= 20 mA –2.5 2.5 Ω

DB1_RON_S On resistance of DEBUG1/2 to C_SBU1/2

= 3.3 V, I

= 20 mA 9.5 17

= 1 V, I

= 20 mA 6.5 12

DB1_ROND_S

On resistance difference between P and N paths of Debug

path DEBUG1/2 to C_SBU1/2

= 1 V to 3.3 V, I

= 20 mA –0.5 0.5 Ω

DB1_TON Switch on time from enable of DEBUG path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

DB1_TOFF Switch off time from disable of DEBUG path

Time from disable bit at charge

pump steady state

500 ns

DB1_BW 3dB bandwidth of DEBUG path C

= 10 pF 200 MHz

DEBUG3/4 MULTIPLEXER PATH

(1)

DB3_RON_U On resistance of DEBUG3/4 to C_USB_TP/TN/BP/BN

= 3.3 V, I

= 20 mA 14 24

= 1 V, I

= 20 mA 9 17

DB3_ROND_U

On resistance difference between P and N paths of

DEBUG3/4 to C_USB_ TP/TN/BP/BN

= 1 V to 3.3V, I

= 20 mA –1.5 1.5 Ω

DB3_RON_S On resistance of DEBUG3/4 to C_SBU1/2

= 3.3 V, I

= 20 mA 9.5 18

= 1 V, I

= 20 mA 6.5 12

DB3_ROND_S

On resistance difference between P and N paths of

DEBUG3/4 to C_SBU1/2

= 1 V to 3.3 V, I

= 20 mA –0.15 0.15 Ω

DB3_TON Switch on time from enable of DEBUG3/4 path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

DB3_TOFF Switch off time from disable of DEBUG3/4 path

Time from disable bit at charge

pump steady state

500 ns

DB3_BW 3dB bandwidth of DEBUG3/4 path C

= 10 pF 200 MHz

TPS65982

ZHCSDS8D –MARCH 2015–REVISED JUNE 2019

www.ti.com.cn

Port Data Multiplexer Switching Characteristics (continued)

Recommended operating conditions; T

= –10 to 85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) The UART switch path connects from the UART buffers to the port pins. See Input/Output (I/O) Characteristics for buffer specifications.

(3) See Port Data Multiplexer USB Endpoint Characteristics for the USB_EP specifications.

LSX_R2P/P2R MULTIPLEXER PATH

(1)

LSX_RON On resistance of LSX_P2R/R2P to C_SBU1/2

= 3.3 V, I

= 20 mA 8.5 17

= 1 V, I

= 20 mA 5.5 11

LSX_ROND

On resistance difference between P and N paths of LSX

path

= 1 V to 3.3 V, I

= 20 mA –0.3 0.3 Ω

LSX_TON Switch on time from enable of LSX path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

LSX_TOFF Switch off time from disable of LSX path

Time from disable bit at charge

pump steady state

500 ns

LSX_BW 3dB bandwidth of LSX path C

= 10 pF 200 MHz

AUX MULTIPLEXER PATH

(1)

AUX_RON On resistance of AUX_P/N to C_SBU1/2

= 3.3 V, I

= 20 mA 3.5 7

= 1 V, I

= 20 mA 2.5 5

AUX_ROND

On resistance difference between P and N paths of

AUX_P/N to C_SBU1/2

= 1 V to 3.3 V, I

= 20 mA –0.25 0.25 Ω

AUX_TON Switch on time from enable of AUX_P/N to C_SBU1/2

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

AUX_TOFF Switch off time from disable of AUX_P/N to C_SBU1/2

Time from disable bit at charge

pump steady state

500 ns

AUX_BW 3dB bandwidth of AUX_P/N to C_SBU1/2 path C

= 10 pF 200 MHz

UART MULTIPLEXER PATH (2

STAGE ONLY)

(1)(2)

UART_RON

On resistance of UART buffers to C_USB_TP/TN/BP/BN or

C_SBU1/2

= 3.3 V, I

= 20 mA 3.1 12 Ω

UART_TON

Switch on time from enable of UART buffer

C_USB_TP/TN/BP/BN or C_SBU1/2 path

Time from enable bit with charge

pump off

150

µs

Time from enable bit at charge

pump steady state

UART_TOFF Switch off time from disable of UART buffer path

Time from disable bit at charge

pump steady state

500 ns

UART_BW 3dB bandwidth of UART buffer path C

= 10 pF 200 MHz

USB_RP MULTIPLEXER PATH

(1)(3)

USB_RON On resistance of USB_RP to C_USB_TP/TN/BP/BN

= 3 V, I

= 20 mA 4.5 10

= 400 mV, I

= 20 mA 3 7

USB_ROND

On resistance difference between P and N paths of

USB_RP to C_USB_TP/TN/BP/BN

= 0.4 V to 3 V, I

= 20 mA –0.15 0.15 Ω

USB_TON Switch on time from enable of USB USB_RP path

Time from enable bit with charge

pump off

150

µs

Time from enable bit at charge

pump steady state

USB_TOFF Switch off time from disable of USB_RP path

Time from disable bit at charge

pump steady state

500 ns

USB_BW 3dB bandwidth of USB_RP path C

= 10 pF 850 MHz

USB_ISO Off Isolation of USB_RP path

= 50 Ω, V

= 800 mV, f = 240

MHz

–19 dB

USB_XTLK Channel to Channel crosstalk of USB_RP path R

= 50 Ω, f = 240 MHz –26 dB

C_SBU1/2 OUTPUT

R_SBU_OPEN Resistance of the open C_SBU1/2 paths V

= 0 V to LDO_3V3 1 MΩ

R_USB_OPEN Resistance of the open C_USB_T/B/P/N paths V

= 0 V to LDO_3V3 1 MΩ

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