提升吞吐率的Polar码Fast-SSCL算法与硬件架构

需积分: 10 62 浏览量更新于2024-09-11 1 收藏 2.11MB PDF 举报

本文档主要探讨了Polar码在高速通信中的应用，特别是针对其高效的译码算法Fast-SSCL（快速Successive Cancellation List）及其相应的硬件架构设计。Polar码是一种最近被发现的具有最优纠错性能的编码方式，尤其在中等长度代码中表现出色。然而，传统的Successive Cancellation Decoding（SCD）虽然能够保证良好的纠错性能，但其解码速度相对较慢，限制了在实时通信中的实际应用。为了提升Polar码的吞吐率，研究者们提出了Fast-SSCL算法。与传统的SCD不同，Fast-SSCL在处理列表大小为2时保持精确性，而对于更大的列表大小，其近似方法带来的错误修正性能损失非常小，通常小于0.05分贝（dB）。这表明，即使牺牲一定的精度，Fast-SSCL也能实现显著的速度提升。文章的核心贡献在于设计了一个基于Fast-SSCL的硬件解码器架构。这个新架构显著提高了Polar码的解码速度，将吞吐率提升了3.16倍，同时只增加了14.2%的硬件占用面积。这样的优化对于现代通信系统中的实时数据传输至关重要，因为它能够在保证服务质量的同时，减少延迟，提高系统的整体效率。硬件实现方面，该设计可能包括并行处理单元、优化的数据流管理和存储结构，以及对Fast-SSCL算法关键步骤的硬件化加速，如利用 Look-Up Tables (LUTs) 减少计算量。此外，为了减小功耗，可能还采用了低能耗技术和资源复用策略。总结来说，这份文档深入研究了Polar码的Fast-SSCL算法在硬件层面的优化，旨在解决实际通信系统中的性能瓶颈问题，为高效、高速的Polar码应用提供了重要的技术支持。这对于推进5G、物联网等通信技术的发展具有重要意义。

2370 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 63, NO. 12, DECEMBER 2016

Fig. 2. SC decoding example for P(8, 4) and {u

, u

}∈F .

β ={β

,β

,...,β

−1

} are passed from a child node to

its parent node. The elements of the left and right messages

={α

,α

,...,α

t−1

−1

} and α

={α

,α

,...,α

t−1

−1

each a vector of 2

t−1

values, are calculated as

= ln



1 + e

+α

i+2

t−1

+ e

i+2

t−1



, (5)

= α

i+2

t−1

+ (1 − 2β

)α

, (6)

while the elements of β, a vector of 2

bits, are computed

using the left and right messages β

={β

,β

,...,β

t−1

−1

}

and β

={β

,β

,...,β

t−1

−1

}



⊕ β

, if i < 2

t−1

i−2

t−1

, otherwise,

(7)

where ⊕ denotes the bitwise XOR and the interval i < 2

t−1

discriminates between bits considered by the left and the right

child. At a leaf node, the i-th bit ˆu

is estimated as

ˆu



0, if i ∈ F or α

≥ 0,

1, otherwise.

(8)

Due to the data dependencies, each node receives α ﬁrst,

then sends α

, receives β

, sends α

, receives β

, and ﬁnally

sends β, in this order. A hardware-friendly version of (5),

proposed in [2], can be written as

= sgn(α

) sgn(α

i+2

t−1

) min(|α

|, |α

i+2

t−1

|), (9)

where

sgn(α

) =



−1, if α

< 0,

1, otherwise.

(10)

C. Fast-SSC Decoding

In SC, the estimation of each bit requires the knowledge of

previously estimated bits. The serial nature of this bit by bit

estimation process limits the speed of SC decoding algorithm.

In order to increase the speed of SC, [6] and [7] observed

four different constituent codes: their decoding can be carried

out in a more efﬁcient way than fully exploring the decoding

tree. These codes are shown in Fig. 2. White circles are Rate-0

nodes, whose leaves consist of frozen bits only, while black

circles are Rate-1 nodes, where all leaves are information

bits. All leaf nodes at t = 0 are either Rate-0 or Rate-1,

being either single frozen bits or single information bits. White

triangles represent Rep nodes, where only the rightmost leaf

is an information bit. Finally, black triangles represent SPC

nodes, i.e., nodes whose leaves are all information bits, except

for the leftmost one. Note that SPC and Rep nodes at t = 1

are equivalent.

Since Rate-0 nodes correspond to frozen bits, they can be

estimated as

= 0. (11)

Rate-1 nodes correspond to all-information bit vectors.

A direct hard estimate based on the LLR values at a Rate-1

node can be carried out as

(

1 − sgn

(

))

. (12)

Rep nodes have one information bit at the leaf branches and

the bit estimate of this information bit is the bit estimate of

all the bits in a Rep node. The LLR value of the information

bit in a Rep node can be calculated as



−1

i=0

. Therefore,

the bit estimates at a Rep node can be found as

⎛

⎝

1 − sgn

⎛

⎝

−1



i=0

⎞

⎠

⎞

⎠

. (13)

SPC nodes have the even-parity constraint. In SC decoding,

this constraint is imposed by checking the hard estimate of

the least reliable bit. If this bit does not satisfy the even-parity

constraint, then it is ﬂipped. The least reliable bit in an SPC

node is found as

min

= arg min

0≤i<2

(|α

|), (14)

and the parity of it is derived as

γ =

−1



i=0



(

1 − sgn

(

))



. (15)

Finally, the bit estimate in an SPC node is calculated as





(

1 − sgn

(

))



⊕ γ, if i = i

min

(

1 − sgn

(

))

, otherwise.

(16)

The advantage of Fast-SSC is that the decoder is optimal,

i.e., it performs exactly as the original SC decoder. Since parts

of the code can be decoded in parallel, Fast-SSC can decode

a received vector with a much higher speed than SC.

D. List Decoding

To improve the error-correction performance of SC for

codes with moderate lengths, the SCL decoding algorithm

estimates a bit with both its possible values 0 and 1. In order

to control the exponential increase in the complexity of this

algorithm, a set of L codeword candidates is memorized at all

times and every new bit estimate produces 2L new candidates,

half of which must be discarded. To this purpose, a Path

Metric (PM) is associated to each codeword candidate (path)

and updated at every new estimation: it can be considered a

cost function, and the L paths with the lowest PMs are allowed

剩余12页未读，继续阅读

gao_jian_

粉丝: 0
资源: 1

提升吞吐率的Polar码Fast-SSCL算法与硬件架构

sscl 自分裂合并

scl_v11.4.rar

inkanet 4.0 recovery image 上汽名爵锐腾车机

matlab中polar码的删余算法

纠错编码原理及MATLAB实现，说明polar码和LDPC码的概述、原理、方法，并通过matlab进行polar码和LDPC码的性能比较

polar码 sc译码 verilog源码

polar码 LDPC码 卷积码误码率

MLC存储 Polar码

给我设计一个含polar码的通信系统 要求 不使用polar码函数库 可以生成SNR图像 在matlab中仿真 把代码写出来

给我设计一个含polar码的通信系统 要求 不使用polar码函数库 可以生成SNR图像 在matlab中仿真

最新资源

polar码 LDPC码卷积码误码率

给我设计一个含polar码的通信系统要求不使用polar码函数库可以生成SNR图像在matlab中仿真把代码写出来

给我设计一个含polar码的通信系统要求不使用polar码函数库可以生成SNR图像在matlab中仿真