没有合适的资源?快使用搜索试试~ 我知道了~
首页Intel Huron River Platform开发指南:Sandy Bridge与Cougar Point结合详解
Intel Huron River Platform开发指南:Sandy Bridge与Cougar Point结合详解
5星 · 超过95%的资源 需积分: 9 7 下载量 122 浏览量
更新于2024-07-24
1
收藏 10.29MB PDF 举报
"Intel Huron River Platform开发指南"
Intel Huron River Platform是英特尔在2010年推出的一款针对移动设备的平台,它主要由第二代Core系列Sandy Bridge处理器和Cougar Point-M平台控制器中枢(PCH)组成。这个平台是英特尔在当时对移动计算领域的一次重要技术更新,旨在提供更高的性能、更好的能效以及增强的多媒体功能。
Sandy Bridge处理器是英特尔酷睿i系列的第二代产品,采用了32纳米工艺制程,集成了图形处理单元(GPU)与CPU核心在同一块硅片上,实现了更高效的系统级集成。这一设计显著提升了处理器的性能和能效,减少了功耗,使得笔记本电脑和其他移动设备拥有更长的电池续航时间。
Cougar Point芯片组作为Huron River Platform的重要组成部分,提供了I/O扩展功能,包括高速数据传输接口如PCI Express、USB和SATA等。它还支持英特尔的高级特性,如Thunderbolt技术(尽管在最初发布时可能未包含)、高清显卡支持和更快的内存控制器,以确保整个系统的流畅运行。
在"Design Guide"中,英特尔详细介绍了如何在Huron River Platform上进行硬件设计和软件开发。这包括了平台的电气特性、机械规格、热设计考虑、电源管理策略以及兼容性的指导。开发者需要遵循这些准则以确保设备的兼容性、稳定性和性能表现。
文档编号436735的这份开发指南强调,尽管提供了详细的设计信息,但英特尔并未授予任何知识产权的许可。此外,英特尔对于其产品的销售或使用不提供任何形式的明示或暗示的保修,包括适用于特定用途、适销性或侵犯任何专利、版权或其他知识产权的保修。
英特尔可能会随时更改产品规格和描述,而无需提前通知。因此,设计者需要密切关注最新的技术更新和修订,以确保他们的设计方案始终符合英特尔的产品要求。此外,Huron River Platform不适合那些设备故障可能导致人身伤害或死亡的应用场景,这是对安全性的明确考虑。
Intel Huron River Platform开发指南是为工程师和开发人员提供了一份全面的参考,帮助他们利用Sandy Bridge处理器和Cougar Point芯片组创建高性能、低功耗的移动计算设备。这份文档不仅包含了硬件设计的详细信息,还涉及了软件优化和系统整合的最佳实践,是开发基于英特尔Huron River Platform产品的关键资源。
16 Intel Confidential Design Guide
301 Decoupling Capacitors Around the Edges of Power Plane ..............................................428
302 Demonstration of Spread Spectrum Clocking (SSC).....................................................429
303 Spectral Comparison of a Clock Scrambled vs. Unscrambled.........................................430
304 An Example of Platform Interference Seen on a Laptop PC ...........................................431
305 FCC Radiation Limit vs. Wireless Noise Specification .................................................... 432
306 Wireless Bands and Their Associated Specifications ..................................................... 432
307 WiMax Radio Target Desense and Platform Noise Requirement ..................................... 433
308 Radio Desense and Platform Noise Level....................................................................434
309 Desense vs. Range Loss ..........................................................................................435
310 Test Setup to Measure Noise at the Antenna .............................................................. 438
311 Test Setup Showing Different Antenna Locations.........................................................438
312 Measured Spectrum at the Antenna on the Base ......................................................... 439
313 Varactor Tuning Circuit to Change the Crystal Frequency .............................................440
314 Results from Probing CK408 and HDD on Intel Laptop .................................................441
315 IEC 61000-4-2 ESD Waveform .................................................................................442
316 Mutual L and C (Lm, Cm) Coupling............................................................................ 443
317 Ground Shape along the I/O Edge of the Board .......................................................... 444
318 WiMAX Optimized Platform Antenna Placement...........................................................449
319 WLAN Platform Antenna Placement ...........................................................................449
320 WiMAX/WWAN Antenna Placement............................................................................450
321 Mini Coaxial Cable Loss per Unit Length.....................................................................452
322 Need for Near Horizon Metrics .................................................................................. 455
323 Antenna Layout and Port Numbering Nomenclature.....................................................459
324 Definition of Angular Components and Axes for the Spherical Coordinate
System (a) and Illustration of Data Points Taken Every 15° in Theta and Phi (b) .............462
325 Flowchart of 3D-PAG Calculation...............................................................................463
326 Z-Axis and Y-Axis Oriented “Donut” Shaped Radiation Pattern ......................................464
327 Uniform Mesh/Sampling of 3D Sphere with Triangles...................................................466
328 Example of Test Bead on a Stub (not preferred) ......................................................... 467
329 Example of differential test bead with matched placement ...........................................467
330 Support for Microstrip test beads ..............................................................................468
331 Support for 3rd layer Stripline (Example with 2 Test Beads) .........................................468
332 Support for (n - 2) layer Stripline (Example with 2 Test Beads...................................... 468
333 Support for 3rd Layer Stripline (Via Added for Probe Placement) ................................... 469
334 TAP Controller (Reference from Boundary Scan Tutorial , Page 32 & Figure 32
by R.G. Ben from Asset-Intertech)............................................................................ 470
335 A Simple Chain Involving 2 Devices ..........................................................................471
336 DFT to Power On CPU Core at ICT.............................................................................474
337 IMVP7 Specific DFT Requirements.............................................................................475
Tables
1 Processor PCI Express Compensation Signal Routing Guideline .......................................37
2 PCI Express Graphics Differential Pair Length Matching ..................................................39
3 PCI Express Graphics Length Matching within a Routing Bundle ......................................40
4 Length Matching within a Routing Bundle.....................................................................41
5 External Graphics PCI Express Differential AC Coupling Capacitor Placement and Matching
Guidelines ...............................................................................................................45
6 External Graphics PCI Express Device Down Routing Guidelines ......................................47
7 External Graphics PCI Express Device Down Short Channel Topology S (2 Via) Routing
Guideline.................................................................................................................48
8 External Graphics PCI Express Add-In Card Guideline for AC Cap on Add-in
Card (C Topology) ....................................................................................................50
9 PCI Express External Graphics Add-In Card Guideline for AC Cap on AIC (D Topology) .......52
10 PCI Express External Graphics Add-In Card Guideline for AC Cap on AIC (E Topology) .......54
Design Guide Intel Confidential 17
11 PCI Express External Graphics Add-In Card Guideline for AC Cap on AIC (F Topology) ....... 56
12 External Graphics PCI Express Add-In Card Reverse Route Topology with AC
Capacitors on AIC (G Topology, 2-VIA and AC Cap on AIC) ............................................ 61
13 External Graphics PCI Express Add-In Card Reverse Route Topology with AC Capacitors on
Motherboard (H Topology, 2-VIA and AC Cap on MB) .................................................... 63
14 External Graphics PCI Express Device Down Reverse Route 2-Via Topology
Routing Guideline..................................................................................................... 65
15 eDP Enable Strap ..................................................................................................... 73
16 Embedded DisplayPort Compensation Signal Routing Guideline ...................................... 73
17 Integrated Graphics eDP Main Link 4-Via Routing Guidelines .......................................... 75
18 Integrated Graphics eDP Main Link 2-Via Trace Length Guidelines................................... 76
19 DisplayPort Main Link for Switchable Graphics Embedded Routing Guidelines ................... 77
20 DisplayPort Main Link for Switchable Graphics Embedded Routing Guidelines ................... 78
21 Integrated Graphics eDP Auxiliary Channel Trace Length Guidelines ................................ 79
22 FDI References ........................................................................................................ 81
23 Intel FDI Signal Groups............................................................................................. 81
24 Intel FDI 3-Via Topology Routing Guidelines ................................................................ 83
25 Intel FDI Short Channel 3-Via Routing Topology Routing Guidelines ................................ 83
26 Intel FDI 4-Via Topology Routing Guidelines ................................................................ 84
27 Disabling Guidelines for External Graphics Designs ....................................................... 86
28 DMI References ....................................................................................................... 87
29 DMI Signal Group..................................................................................................... 87
30 DMI 3-Via Topology Routing Guidelines ....................................................................... 89
31 DMI Short Channel 3-Via Topology Routing Guidelines .................................................. 90
32 DDR3 References ..................................................................................................... 92
33 DDR3 Dual-Channel Signal Groups ............................................................................. 92
34 DDR3 Length Matching ........................................................................................... 100
35 DDR3 Clock Signal Group Routing Guidelines ............................................................. 102
36 DDR3 Control Signal Group Routing Guidelines (Dual Channel)..................................... 103
37 DDR3 Command Signal Group Routing Guidelines (Dual Channel)................................. 105
38 DDR3 Data Signal Group Routing Guidelines (Dual Channel) ........................................ 106
39 DDR3 Data Strobe Signal Group Routing Guidelines (Dual Channel) .............................. 107
40 DDR3 Processor Compensation Guidelines ................................................................. 108
41 S3 Power Reduction Circuit Signal Description............................................................ 111
42 Asynchronous Legacy Signal Group .......................................................................... 116
43 Asynchronous Signal General Routing Guideline ......................................................... 117
44 PROCHOT# Routing Guidelines ................................................................................ 118
46 PROCHOT# with 2VR Routing Guidelines ................................................................... 119
45 PROCHOT# with 2VR Routing Guidelines ................................................................... 119
47 PECI Routing Guidelines.......................................................................................... 120
48 PWRGOOD Routing Guidelines ................................................................................. 121
49 THERMTRIP# Routing Guidelines.............................................................................. 122
50 BPM# [7:0] Routing Guidelines ................................................................................ 122
51 PMSYNC# Routing Guidelines .................................................................................. 123
52 RESET# Routing Guideline ...................................................................................... 123
53 SM_DRAMPWROK with DDR Power Gating Routing Guideline........................................ 125
54 SM_DRAMPWROK without DDR Power Gating Guideline ............................................... 126
55 Platform Input Power Management Checklist.............................................................. 130
56 Digital Display Interface Reference Documents........................................................... 133
57 Digital Display Ports Enable and Disable Guidelines..................................................... 133
58 Configuration Pin Mapping for DDI Ports.................................................................... 134
59 DisplayPort Main Link 4-Via External on Motherboard Routing Guidelines ....................... 138
60 DisplayPort Main Link 2-Via External on Motherboard Routing Guidelines ....................... 139
61 DisplayPort Main Link for External on Docking Routing Guidelines ................................. 140
62 DisplayPort Main Link for Switchable Graphics External Routing Guidelines..................... 142
18 Intel Confidential Design Guide
63 DisplayPort Main Link for Switchable Graphics Docking Routing Guidelines .....................143
64 DIsplayPort AUX-CH Differential Pair Length Matching Table.........................................146
65 DisplayPort Auxiliary Channel Routing Guidelines ........................................................ 146
66 DIsplayPort AUX-CH Differential Pair Length Matching Table.........................................147
67 DisplayPort Auxiliary Channel Routing Guidelines ........................................................ 148
68 HDMI Differential Pair Length Matching Table .............................................................152
69 HDMI Cost Reduced Level Shifter Motherboard Topology for Max Data
Rate of 1.65 Gb/s - Routing Guidelines...................................................................... 153
70 HDMI Active Level shifter Motherboard Topology for Max Data Rate of
2.225 Gb/s - Routing Guidelines ............................................................................... 154
71 HDMI Data and Clock Active Level shifter Docking Topology Max Data
Rate of 2.225 Gb/s - Routing Guidelines ....................................................................155
72 HDMI Trace Length Guidelines for Data and Clock Switchable Graphics
for Max Data Rate of 2.225 Gb/s - Routing Guidelines ................................................. 157
73 HDMI Trace Length Guidelines for Data and Clock Switchable Graphics
Docking Topology for Max Data Rate of 2.225 Gb/s - Routing Guidelines........................158
74 HDMI DDC Signals on Motherboard Topology Routing Guideline .................................... 159
75 HDMI DDC Over the Dock Trace Length Guidelines......................................................161
76 SDVO Differential Pair Length Matching Table.............................................................164
77 SDVO 3-Via Device Down on Motherboard Trace Length Guidelines ...............................165
78 SDVO ADD2 Card Trace Length Guidelines .................................................................166
79 SDVO Control Bus Device Down on Motherboard Routing Guidelines .............................. 167
80 SDVO Control Bus ADD2CARD Topology Routing Guidelines..........................................168
81 CRT DAC Signal List ................................................................................................ 171
82 CRT DAC Video Filter Component Descriptions............................................................ 172
83 Analog RGB/CRT Length Matching Guidelines ............................................................. 174
84 CRT DAC Trace Geometry ........................................................................................174
85 CRT DAC Device Down on Motherboard Topology Layer Transition Guidelines ................. 175
86 CRT DAC Device Down on Motherboard Topology Routing Guidelines ............................. 176
87 CRT DAC Docking Topology Layer Transition Guidelines ............................................... 176
88 CRT DAC Docking Topology General Routing Guidelines ............................................... 177
89 CRT DAC Docking Topology Routing Guidelines........................................................... 177
90 CRT DAC Switchable Graphics Device Down on Motherboard Topology Layer Transition
Guidelines .............................................................................................................179
91 CRT DAC Switchable Graphics Device Down on Motherboard Topology
Routing Guidelines..................................................................................................179
92 CRT DAC Switchable Graphics Docking Topology Layer Transition Guidelines ..................180
93 CRT DAC Switchable Graphics Docking Topology Routing Guidelines .............................. 181
94 CRT Sync Trace Geometry ....................................................................................... 182
95 CRT SYNC Device Down on Motherboard Layer Transition Guidelines ............................. 183
96 CRT SYNC Device Down on Motherboard Trace Length Guidelines .................................183
97 CRT SYNC Docking Layer Transition Guidelines ...........................................................184
98 CRT SYNC Docking Routing Guideline ........................................................................184
99 CRT SYNC Docking Trace Length Guidelines Topology.................................................. 185
100 CRT SYNC Switchable Graphics Dock Topology Layer Transition Guidelines.....................186
101 CRT SYNC Switchable Graphics Dock Topology Trace Length Guidelines ......................... 187
102 CRT SYNC Switchable Graphics Dock Topology Layer Transition Guidelines.....................188
103 CRT SYNC Switchable Graphics Dock Topology Trace Length Guidelines ......................... 188
104 CRT Control Signal Routing Guidelines.......................................................................189
105 LVDS Signal Group and Signal Pair Names .................................................................191
106 LVDS Differential Pair Length Matching ...................................................................... 192
107 LVDS Direct Connect Layer Transition Guidelines ........................................................193
108 LVDS Direct Connect Trace Length Guidelines.............................................................193
109 LVDS Switchable Graphics Topology Routing Guidelines ...............................................194
110 LVDS Control Bus Trace Length Guidelines .................................................................195
Design Guide Intel Confidential 19
111 External Graphics (PCH Integrated Graphics Disable) .................................................. 198
112 PCI Express Expansion Reference Documents ............................................................ 201
113 PCI Express Signal Groups ...................................................................................... 201
114 PCI Express Expansion Length Matching.................................................................... 204
115 PCI Express Device Down at 2.5 GT/s Routing Guidelines ............................................ 206
116 PCI Express Device Down 5 GT/s Routing Guidelines................................................... 207
117 PCI Express Docking 2.5 GT/s Routing Guidelines....................................................... 210
118 PCI Express Docking 5 GT/s Routing Guidelines.......................................................... 211
119 ExpressCard/ PCI Express Mini-Card 2.5 GT/s Topology Routing Guidelines.................... 215
120 ExpressCard/ PCI Express Mini-Card 5 GT/s Routing Guidelines .................................... 216
121 ExpressCard/Mini-Card at 2.5 GT/s on Docking Routing Guidelines ............................... 218
122 ExpressCard/Mini-Card and on Docking at 5 GT/s Topology Trace Length Guidelines ....... 219
123 USB References ..................................................................................................... 221
124 USB 2.0 Signal Groups............................................................................................ 221
125 USB 2.0 Test Points and Probing .............................................................................. 222
126 USB 2.0 Differential Pair Length Matching Table ......................................................... 222
127 USB 2.0 External Routing Guidelines (with Common Mode Choke and
ESD Protection Diode) ............................................................................................ 223
128 USB 2.0 Docking Station Routing Guidelines (with Common Mode
Choke and ESD Protection Diode)............................................................................. 225
129 USB 2.0 Overcurrent Pin Default Usage..................................................................... 231
130 USB 2.0 Overcurrent Pin Example Configuration......................................................... 231
131 Intel ME-EC Interaction Signal List with and without M3 Support .................................. 235
132 Power Delivery Summary for Intel Management Engine SubSystem .............................. 240
133 Intel AMT Controller Link Signals.............................................................................. 242
134 Controller Link Topology - To WLAN (CL_CLK1, CL_DATA1, CL_RST1#) Guidelines.......... 243
135 PCH CMOS Signal Description .................................................................................. 244
136 Serial Peripheral Interface Signal Description ............................................................. 247
137 SPI Length Matching Guidelines ............................................................................... 247
138 SPI Single Flash Device Routing Guidelines................................................................ 248
139 SPI Dual Device MOSI Routing Guidelines.................................................................. 250
140 SPI Dual Device MISO Routing Guidelines.................................................................. 250
141 SPI Dual Device SPI_CS0/1# Routing Guidelines ........................................................ 250
142 SPI Dual Device SPI_CLK Routing Guidelines ............................................................. 251
143 Strapping Options Flash .......................................................................................... 251
144 Firmware Hub Interface Signal Description ................................................................ 253
145 FWH V
PP
Isolation Circuitry...................................................................................... 253
146 Intel HD Audio Signals ............................................................................................ 254
147 Intel HD Audio HDA_SDIN Audio Down Routing Guidelines........................................... 255
148 Layout Recommendations for HDA_SDIN Audio Down Docking Topology........................ 255
149 Layout Recommendations for HDA_SDO/HDA_SYNC/HDA_BCLK/HDA_RST# Mobile Star
Routing Guidelines ................................................................................................. 257
150 HDA_DOCK_EN# Star Topology Routing Guidelines .................................................... 258
151 HDA_SDO/HDA_SYNC/HDA_BCLK/HDA_RST# Mobile Branched Routing Guidelines ......... 259
152 HDA_DOCK_EN# for Branch Routing Guidelines ........................................................ 259
153 Test interface Signals ............................................................................................. 261
154 RTC Signals........................................................................................................... 263
155 RTC Routing Guidelines........................................................................................... 264
156 SMBus and SMlink Signals....................................................................................... 269
157 SMBus Routing Summary........................................................................................ 273
158 SMBus Length Matching Guidelines........................................................................... 273
159 Bus Capacitance Reference Chart ............................................................................. 273
160 Bus Capacitance/Pull-up Resistor Relationship............................................................ 274
161 Frequency Sensitivity ............................................................................................. 275
162 SMBus Data Signals on the PCH ............................................................................... 282
20 Intel Confidential Design Guide
163 PCIe Data Signals on the PCH .................................................................................. 283
164 Clock and Reset Signals on the PCH ..........................................................................283
165 PCIe and SMBus Modes ........................................................................................... 285
166 Third-Party Magnetics Modules for GbE......................................................................287
167 Integrated Magnetics Recommended Qualification Criteria............................................288
168 LAN Switch ............................................................................................................ 289
169 LED Default Values .................................................................................................289
170 MDI Routing Summary ............................................................................................ 300
171 Maximum Trace Lengths Based on Trace Geometry and Board Stack-Up ........................301
172 Capacitor Stuffing Option Recommended Values ......................................................... 308
173 Crystal Manufacturers and Part Numbers ...................................................................311
174 Oscillator Manufacturers and Part Numbers ................................................................ 315
3-175LAN Switch Manufacturers and Part Numbers ...........................................................316
176 SATA References .................................................................................................... 320
177 SATA Signal Groups ................................................................................................320
178 SATA Differential Pair Length Matching Table..............................................................321
179 SATA Differential Pair Trace Spacing Guidelines .......................................................... 322
180 AC Coupling Capacitor.............................................................................................322
181 SATAICOMPO/SATAICOMPI and SATA3RCOMPO/SATA3COMPI for Mobile
Stack-Up Routing Guidelines .................................................................................... 323
182 SLOAD/SGPIOCLK and SDATAOUT0/1 for Mobile Stack-Up Routing Guidelines ................325
183 SATA or mSATA Differential-Pair for Mobile Stack-Up – Direct Connect
Routing Guidelines..................................................................................................326
184 SATA Differential-Pair Routing Guidelines for Mobile Stack-Up with
Flex Cable Topology................................................................................................327
185 SATA Differential-Pair Routing Guidelines for Mobile Docking Topology...........................328
186 SATA Differential-Pair Routing Guidelines for Mobile Docking with Repeater Topology ......329
187 SATA Gen3 Direct Connect Topology Routing Guidelines .............................................. 330
188 eSATA Differential-Pair Routing Guidelines .................................................................331
189 eSATA with Repeater Routing Guidelines....................................................................332
190 eSATA on Docking Station with Repeater Routing Guidelines ........................................333
3-191SATA 6 Gb/s Transitional Via Layout Recommendations ............................................. 337
192 TPM Signals ........................................................................................................... 338
193 Motherboard Stack-Up Parameter Values (Microstrip - 4-mils (0.102 mm) Nominal Trace
Width) ..................................................................................................................343
194 Motherboard Stack-Up Parameter Values (Stripline) .................................................... 344
195 Motherboard Stack-Up Parameter Values (8-Layer / 10-Layer Dual-Stripline) .................345
196 Breakout Geometries for Various I/O Interfaces..........................................................352
197 Single-ended and Differential Targets for Microstrip Routing .........................................353
198 Single-ended and Differential Impedance Targets for Stripline Routing........................... 354
199 Single-ended and Differential Targets for 8-layer / 10-layer Dual-Stripline Routing.......... 355
200 General Differential Pair Length Matching................................................................... 361
201 Max Root Square Sum (RSS) Length vs. Transfer Speed ..............................................366
202 Clock Group References...........................................................................................370
203 Clock Groups .........................................................................................................371
204 Host Clock to Processor Routing Guidelines ................................................................376
205 33-MHz Clock Output group Routing Guidelines ..........................................................378
206 Loop Back Clock Routing Guideline............................................................................379
207 SRC/SRC# Device Down Routing Guidelines...............................................................380
208 SRC/SRC# Add-In Card Routing Guidelines ................................................................382
209 FLEX Clock Routing Guideline ................................................................................... 383
210 Switchable Graphics Muxing Display Interfaces Hardware Requirements.........................389
211 Switchable Graphics GPIO Requirements ...................................................................390
212 CRT DAC Signal Listing............................................................................................395
213 GPIO Selection Criteria for Motherboard Down dGPU Solution .......................................403
剩余476页未读,继续阅读
2011-10-22 上传
点击了解资源详情
2021-05-02 上传
2021-06-29 上传
2012-12-13 上传
2021-09-25 上传
2021-04-22 上传
点击了解资源详情
点击了解资源详情
polson
- 粉丝: 0
- 资源: 1
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- NIST REFPROP问题反馈与解决方案存储库
- 掌握LeetCode习题的系统开源答案
- ctop:实现汉字按首字母拼音分类排序的PHP工具
- 微信小程序课程学习——投资融资类产品说明
- Matlab犯罪模拟器开发:探索《当蛮力失败》犯罪惩罚模型
- Java网上招聘系统实战项目源码及部署教程
- OneSky APIPHP5库:PHP5.1及以上版本的API集成
- 实时监控MySQL导入进度的bash脚本技巧
- 使用MATLAB开发交流电压脉冲生成控制系统
- ESP32安全OTA更新:原生API与WebSocket加密传输
- Sonic-Sharp: 基于《刺猬索尼克》的开源C#游戏引擎
- Java文章发布系统源码及部署教程
- CQUPT Python课程代码资源完整分享
- 易语言实现获取目录尺寸的Scripting.FileSystemObject对象方法
- Excel宾果卡生成器:自定义和打印多张卡片
- 使用HALCON实现图像二维码自动读取与解码
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功