TI-TLV1548-EP/pdf数据手册：高 temperatura 10位ADC Converter

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SGLS171A − JUNE 2003 − REVISED DECEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

input data bits

DATA IN is internally connected to a 4-bit serial input data register. The input data selects a different mode or

selects different analog input channels. The host provides the data word with the MSB first. Each data bit clocks

in on the edge (rising or falling depending on the status of INV CLK

and FS) of the I/O CLK sequence. The input

clock can be inverted by grounding INV CLK

(see Table 3 for the list of software programmed operations set

by the input data).

Table 3. TLV1548 Software-Programmed Operation Modes

INPUT DATA BYTE

FUNCTION SELECT

A3 − A0

COMMENT

FUNCTION SELECT

BINARY HEX

COMMENT

Analog channel A0 for TLV1548 selected 0000b 0h

Analog channel A1 for TLV1548 selected 0001b 1h

Analog channel A2 for TLV1548 selected 0010b 2h

Analog channel A3 for TLV1548 selected 0011b 3h

Analog channel A4 for TLV1548 selected 0100b 4h

Analog channel A5 for TLV1548 selected 0101b 5h

Analog channel A6 for TLV1548 selected 0110b 6h

Analog channel A7 for TLV1548 selected 0111b 7h

Software power down set 1000b 8h No conversion result (cleared by any access)

Fast conversion rate (10 µs) set 1001b 9h No conversion result (cleared by setting to fast)

Slow conversion rate (40 µs) set 1010b Ah No conversion result (cleared by setting to slow)

Self-test voltage (V

ref)

− V

ref−

)/2 selected 1011b Bh Output result = 200h

Self-test voltage V

ref*

selected 1100b Ch Output result = 000h

Self-test voltage V

ref)

selected 1101b Dh Output result = 3FFh

Reserved 1110b Eh No conversion result

Reserved 1111b Fh No conversion result

analog inputs and internal test voltages

The eight analog inputs and the three internal test inputs are selected by the 11-channel multiplexer according

to the input data bit as shown in Table 3. The input multiplexer is a break-before-make type to reduce

input-to-input noise injection resulting from channel switching.

The device can be operated in two distinct sampling modes: normal sampling mode (fixed sampling time) and

extended sampling mode (flexible sampling time). When CSTART

is held high, the device is operated in normal

sampling mode. When operated in normal sampling mode, sampling of the analog input starts on the rising edge

of the fourth I/O CLK pulse in the microprocessor interface mode (and on the fourth falling edge of I/O CLK in

the DSP interface mode). Sampling continues for 6 I/O CLK periods. The sample is held on the falling edge of

the tenth I/O CLK pulse in the microprocessor interface mode. The sample is held on the falling edge of the tenth

I/O CLK pulse in the DSP interface mode.The three test inputs are applied to the multiplexer, then sampled and

converted in the same manner as the external analog inputs.

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SGLS171A − JUNE 2003 − REVISED DECEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

converter

The CMOS threshold detector in the successive-approximation conversion system determines the value of

each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase

of the conversion process, the analog input is sampled by closing the S

switch and all S

switches

simultaneously. This action charges all of the capacitors to the input voltage.

In the next phase of the conversion process, all S

and S

switches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF −)

voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and

then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector

looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF −. If the voltage at the summing

node is greater than the trip point of the threshold detector (approximately one-half V

), a bit 0 is placed in the

output register and the 512-weight capacitor is switched to REF −. If the voltage at the summing node is less

than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight capacitor remains

connected to REF + through the remainder of the successive-approximation process. The process is repeated

for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the

capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

Threshold

Detector

Node 512

REF−

REF+

512

To Output

Latches

REF−

REF+

REF−

REF+

REF−

REF+

REF−

REF+

REF−

REF+

REF−

11248128256

REF−

Figure 1. Simplified Model of the Successive-Approximation System

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