ATmega2564RFR2：低功耗2.4GHz微控制器

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"ATmega2564RFR2是一款由Atmel公司（现已被Microchip Technology收购）生产的微控制器，结合了高性能、低功耗的AVR 8位微控制器与2.4GHz无线传输功能，适用于ZigBee和IEEE 802.15.4网络。该芯片具有硬件辅助的多PAN地址过滤，能够实现网络支持并降低功耗。" 在这款微控制器中，以下是一些关键特性： 1. **高级硬件辅助减少功率消耗**：设计中包含功能，可以在不牺牲性能的情况下降低能耗，这对于电池供电或对能效有高要求的应用来说非常关键。 2. **高性能，低功耗AVR RISC架构**：采用135条强大的指令集，大部分指令在一个时钟周期内执行，提供高达16 MIPS的吞吐量。它能在16MHz频率下运行，并在1.8V电压下保持全静态操作。 3. **非易失性程序和数据存储器**： - **闪存**：提供256KB/128KB/64KB的可在线自编程闪存，耐久性强，可在125°C下进行10,000次写/擦除操作，而在85°C下可达到25,000次。 - **EEPROM**：包括8KB/4KB/2KB的EEPROM，耐久性同样出色，125°C下可承受20,000次写/擦除，而25°C下则可达100,000次。 4. **内部SRAM**：具备32KB/16KB/8KB的高速内部静态RAM，用于临时数据存储和处理。 5. **JTAG接口**：符合IEEE 1149.1标准，提供边界扫描能力，同时支持广泛的片上调试支持，包括通过JTAG接口对闪存、EEPROM、熔丝和锁存器进行编程。 6. **硬件辅助的网络支持**：通过硬件辅助的多PAN地址过滤，ATmega2564RFR2可以有效地处理多个个人区域网络（PAN），提高网络效率和可靠性。 7. **2.4GHz无线传输**：集成的2.4GHz收发器允许设备参与ZigBee和IEEE 802.15.4标准的无线通信，这些协议常用于物联网(IoT)、家庭自动化和无线传感器网络等应用。 8. **其他功能**：还包含了32个8位通用工作寄存器，以及一个2周期乘法器，增强了计算能力。这些特性使得ATmega2564RFR2成为需要高性能、低功耗、无线通信能力和强大内存管理的嵌入式应用的理想选择，如智能家居、远程监控、工业自动化等领域。开发人员可以利用其丰富的外设集和强大的处理能力来创建高效、节能的系统。

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ATmega2564/1284/644RFR2

interrupts are assigned individual enable bits which must be written logic one together

with the Global Interrupt Enable bit in the Status Register in order to enable the

interrupt. Depending on the Program Counter value, interrupts may be automatically

disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves

software security. See the section

"Memory Programming" on page 502 for details.

The lowest addresses in the program memory space are by default defined as the

Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on

page 241. The list also determines the priority levels of the different interrupts. The

lower the address the higher is the priority level. RESET has the highest priority, and

next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to

the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register

(MCUCR). Refer to "Interrupts" on page 241 for more information. The Reset Vector

can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see "Memory Programming" on page 502.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts

are disabled. The user software can write logic one to the I-bit to enable nested

interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit

is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that

sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the

actual Interrupt Vector in order to execute the interrupt handling routine, and hardware

clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a

logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while

the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and

remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if

one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared,

the corresponding Interrupt Flag(s) will be set and remembered until the Global

Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present.

These interrupts do not necessarily have Interrupt Flags. If the interrupt condition

disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and

execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt

routine, nor restored when returning from an interrupt routine. This must be handled by

software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately

disabled. No interrupt will be executed after the CLI instruction, even if it occurs

simultaneously with the CLI instruction. The following example shows how this can be

used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

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ATmega2564/1284/644RFR2

8 AVR Memories

This section describes the different memories in the ATmega2564/1284/644RFR2. The

AVR architecture has two main memory spaces, the Data Memory and the Program

Memory space. In addition, the ATmega2564/1284/644RFR2 features an EEPROM

Memory for data storage. All three memory spaces are linear and regular.

8.1 In-System Reprogrammable Flash Program Memory

The ATmega2564/1284/644RFR2 contains FLASH_SIZE Bytes On-chip In-System

Reprogrammable Flash memory for program storage, see

Figure 8-6 below. Since all

AVR instructions are 16 or 32 bits wide, the Flash is 16 bit wide. For software security,

the Flash Program memory space is divided into two sections, Boot Program section

and Application Program section.

The Flash memory has an endurance of at least 2000 write/erase cycles. The

ATmega2564/1284/644RFR2 Program Counter (PC) is 16 bits wide, thus addressing

the required program memory locations. The operation of Boot Program section and

associated Boot Lock bits for software protection are described in detail in "Boot Loader

Support – Read-While-Write Self-Programming" on page 485. "Memory Programming"

on page 502 contains a detailed description on Flash data serial downloading using the

SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see

the LPM – Load Program Memory instruction description and ELPM – Extended Load

Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in "Instruction

Execution Timing" on page 15.

Figure 8-6. Program Flash Memory Map

Boot Flash Section

Program Memory

Application Flash Section

$0000

The application section of the Flash memory contains 3 user signature pages. These

pages can be used to store data that should never be modified by an application

program e.g. ID numbers, calibration data etc. For details see section "User Signature

Data" on page 505.

8.2 SRAM Data Memory

Figure 8-7 on page 19 shows how the ATmega2564/1284/644RFR2 SRAM Memory is

organized. The ATmega2564/1284/644RFR2 is a complex microcontroller with more

peripheral units than can be supported within the 64 location reserved in the Opcode for

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ATmega2564/1284/644RFR2

Figure 8-8. On-Chip Data SRAM Access Cycles

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction



Next Instruction

8.3 EEPROM Data Memory

The ATmega2564/1284/644RFR2 contains EEPROM_SIZE Bytes of data EEPROM

memory. It is organized as a separate data space. Read access is byte-wise. The

access between the EEPROM and the CPU is described in the following, specifying the

EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,

see "Serial Downloading" on page 519, "Programming via the JTAG Interface" on page

523, and "Programming the EEPROM" on page 533 respectively.

8.3.1 EEPROM Read Write Access

The EEPROM Access Registers are accessible in the I/O space, see "EEPROM

The write access time for the EEPROM is given in Table 8-3 below. A self-timing

function, however, lets the user software detect when the next byte can be written. If the

user code contains instructions that write the EEPROM, some precautions must be

taken. In heavily filtered power supplies, DVDD is likely to rise or fall slowly on power-

up/down. This causes the device for some period of time to run at a voltage lower than

specified as minimum for the clock frequency used. See "Preventing EEPROM

Corruption" on page 26 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be

followed. See the description of the EEPROM Control Register for details on this,

"EEPROM Register Description" on page 26.

When the EEPROM is read, the CPU is halted for four clock cycles before the next

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before the next instruction is executed.

The calibrated oscillator is used to time the EEPROM accesses. The following table

lists the typical programming time for EEPROM access from the CPU.

Table 8-3. EEPROM Programming Time

Symbol Typical Programming time

EEPROM write (from CPU) 4.5 ms

EEPROM erase (from CPU) 8.5 ms

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