JSFCBx3Y7ABBx系列：4Gbit NAND Flash + 2Gbit LPDDR2 MCP详细规格

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"JSFCBx3Y7ABBx-4xx_rev1.0_4G(4bit+ECC)_2G(LPDDR2)_Full.pdf" 描述了一个内存组件，具体是JSFCB系列的多芯片封装(MCP)产品，包含4GB 4位ECC NAND闪存和2GB LPDDR2动态随机存取存储器。该文档详细介绍了MCP的规格和历史修订。设备名称以JSFCB开头，后跟不同的字母和数字组合，例如JSFCBB3Y7ABBG-425C和JSFCBD3Y7ABBD-425D，这些表示不同的密度和组织结构。NAND闪存部分提供了4GB的存储容量，支持4位ECC（错误校验码），确保数据的可靠性和稳定性。ECC技术能够在检测到错误时进行纠正，提高系统的稳定性。 NAND闪存有两种组织结构：x8和x32，分别代表每个总线周期可以传输8位或32位数据。对于SLC+（单级单元）NAND闪存，它比传统的SLC具有更高的密度，同时在读写速度上可能有所妥协，但保持了高耐用性。 LPDDR2（低功耗双倍数据速率同步动态随机存取存储器）是用于移动设备的一种内存类型，以1.8V/1.2V的电压运行，旨在降低功耗。内存密度为2GB，同样有x32的数据宽度，适合高速数据处理。LPDDR2相比标准DDR内存更适合移动设备，因为它能更有效地管理能源。封装类型为162球BG（球栅阵列）封装，尺寸分别为8x10.5x0.8mm和11.5x13.5x0.9mm，表明了MCP的物理大小。不同版本的封装尺寸可能适用于不同的应用场景，例如空间有限的便携式设备。文档还提到了操作温度范围，包括商业级的0℃至70℃和扩展级的25℃至85℃，这意味着这些组件可以在各种环境条件下稳定工作。修订历史显示了文档从2014年3月到2015年2月的多次更新，涉及到NAND数据表的更新、封装尺寸的添加以及中间体标识的变更，反映了产品设计和规格的不断优化和完善。这个MCP产品是针对需要高效能、低功耗存储解决方案的设备设计的，比如智能手机、平板电脑或其他移动设备。其结合了高容量的NAND闪存和快速的LPDDR2内存，提供了一种集成的存储解决方案，兼顾数据的可靠性和系统的响应速度。

JSF(A/C)xxxN7xB

1Gb/4Gb 4bit ECC NAND FLASH

Figure 1.5 Array Organization — JSFCxxxN7xB (x8)

Figure 1.6 Array Organization — JSFCxxxN7xB (x16)

Rev 2.0 / Jan. 2015

JSF(A/C)xxxN7xB

1Gb/4Gb 4bit ECC NAND FLASH

There

are

six

standard

bus

operations

that

control

the

device

Command

Input

Address

Input

Data

2. Bus Operation

There

are

six

standard

bus

operations

that

control

the

device

Command

Input

Address

Input

Data

Input, Data Output, Write Protect, and Standby. (See Table 1.4.)

Typicallyglitcheslessthan5nsonChipEnable,WriteEnable,andReadEnableareignoredbythe

memory and do not affect bus operations.

2.1 Command Input

The Command Input bus operation is used to give a command to the memory device. Commands are

accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read

Enable

high

and

latched

the

rising

edge

Write

Enable

Moreover,

for

commands

that

start

Enable

high

and

latched

the

rising

edge

Write

Enable

Moreover,

for

commands

that

start

modify operation (program/erase) the Write Protect pin must be high. See Figure 6.1 and Table 5.4

for details of the timing requirements. Command codes are always applied on I/O7:0 regardless of

the bus configuration (x8 or x16).

2.2 Address Input

The Address Input bus operation allows the insertion of the memory address. For the JSFCxxxN7xB

device, five write cycles are needed to input the addresses. For the JSFAxxxN7xB, four write cycles

are needed to input the addresses. If necessary, a 5th dummy address cycle can be issued to

JSFAxxxN7xB, which will be i

nored by the NAND device without causin

problems. Addresses are

accepted with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read

Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a

modify operation (program/erase) the Write Protect pin must be high. See Figure 6.2 and Table 5.4

for details of the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus

configuration (x8 or x16). Refer to Table 1.3-1 through Table 1.3-2 for more detailed information.

2.3 Data Input

The

Data

Input

bus

operation

allows

the

data

programmed

sent

the

device

The

data

The

Data

Input

bus

operation

allows

the

data

programmed

sent

the

device

The

data

insertion is serial and timed by the Write Enable cycles. Data is accepted only with Chip Enable low,

Address Latch Enable low, Command Latch Enable low, Read Enable high, and Write Protect high and

latched on the rising edge of Write Enable. See Figure 6.3 and Table 5.4 for details of the timing

requirements.

2.4 Data Output

The Data Output bus operation allows data to be read from the memory array and to check the

Status

content,

and

the

data

Data

can

serially

shifted

out

toggling

the

Read

Status

content,

and

the

data

Data

can

serially

shifted

out

toggling

the

Read

Enable pin with Chip Enable low, Write Enable high, Address Latch Enable low, and Command Latch

Enable low. See Figure 6.4 and Table 5.4 for details of the timings requirements.

2.5 Write Protect

The Hardware Write Protection is activated when the Write Protect pin is low. In this condition,

modify operations do not start and the content of the memory is not altered. The Write Protect pin is

not latched by Write Enable to ensure the protection even during power up.

2.6 Standby

In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.

Rev 2.0 / Jan. 2015

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