CH7036A-BF：LVDS转HDMI/VGA芯片，支持1366X768分辨率

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"CH7036A-BF是一款视频信号转换芯片，它可以将LVDS（Low Voltage Differential Signaling）信号转换为HDMI或VGA信号，并且具有BYPASS功能，可以保持原始LVDS信号的输出。该芯片支持的最大输入分辨率是1366X768。" 详细说明: CH7036是由Chrontel公司制造的一款RGB/HDMI/LVDS编码器，主要用于视频信号的转换和处理。以下是对这款芯片的详细特点和功能的解析： 1. **LVDS接收与传输**：CH7036能处理单通道18位/24位的LVDS信号，最高支持1366x768分辨率的显示输出。 2. **HDMI编码**：该芯片内置的HDMI编码器可支持高达1080p的高清视频输出，满足高清电视和显示器的需求。 3. **VGA支持**：除了HDMI，它还支持VGA接口，同样可达到1080p的分辨率，适应不同类型的显示设备。 4. **HDMI重传功能**：CH7036还具备HDMI重传功能，可作为HDMI信号的中继器，增强信号传输距离。 5. **DDC和EDID**：支持DDC（Display Data Channel）主控，用于读取EDID（Extended Display Identification Data），实现显示器自动识别和配置。 6. **Hot Plug Detection**：支持HDMI/DVI的热插拔检测，能实时监测设备连接状态。 7. **HDCP兼容**：可选配HDCP 1.1版功能，提供数字内容保护。 8. **高速DAC**：内含三个10位高速数模转换器，确保高质量的图像输出。 9. **DAC开关及复合同步**：通过内部寄存器编程，可以控制DAC的开关，并支持分离的复合同步信号。 10. **连接状态检测**：芯片能检测显示器的连接情况，用户可通过内部寄存器查询连接状态。 11. **像素级色彩增强**：仅对模拟RGB输入提供亮度和对比度的像素级增强功能。 12. **音频接口**：支持SPDIF音频接口，可处理最高20位数据流，192kHz/2声道的音频信号。 13. **I2S数字音频输入**：支持I2S接口，能接收最高24位数据流，频率范围包括32kHz、44.1kHz、48kHz、88.2kHz、96kHz、176.4kHz和192kHz，均为2声道。 14. **帧缓冲**：集成的帧缓冲允许输入的LVDS视频时序有较大的灵活性。 15. **视频帧转换**：芯片能够转换输入的视频帧率，适应不同的显示需求。 CH7036A-BF是实现多种视频信号转换的理想解决方案，适用于需要在不同显示标准间切换的系统中，如多媒体播放器、电视盒、电脑显卡等。它的多样性和高分辨率支持使其在高清视频处理领域具有广泛的应用价值。

CHRONTEL

CH7036

201-1000-009 Rev. 1.24, 08/15/2011 11

The CH7036 supports 32k/2ch, 44.1kHz/2ch, 48kHz/2ch, 88.2kHz/2ch, 96kHz/2ch, 176.4kHz/2ch and 192kHz/2ch

SPDIF input, and the maximum signal data width is up to 20 bits (Refer to Figure 5 for SPDIF interface format).

To select the S/PDIF audio input format, the bit-6 of the offset 1Eh - Register Page 1 needs to set to “1”; the bit-0 of

the offset 07h - Register Page 1 will also need to be switched to “0” to power on the decoder. The CH7036 audio

decoder is cable of detecting incoming S/PIDF frequency and dynamically sampling the audio stream.

Frame 191 Frame 0 Frame 1 Frame 191 Frame 0

W B W M

Preamble Auxiliary LSB MSB U V C P

0 3 4 7 8 11 12 27 28 31

16-bit of bitstream

1 block = 192 Frame

Figure 5: SPDIF interface format

2.2.2 I2S Input

The I

S Bus (Inter-IC Sound [I2S]) is another digital audio format supported by CH7036. This serial bus audio

interface consists of three serial bus lines: a line with data channel [SD], a word select line [WS], and a clock line

[SCK]. Data is transmitted in two's complement, MSB first.

The built-in I

S decoder supports the following encode formats

1. Left-justified I2S mode, 16bits/20bits/24bit

2. Right-justified I2S mode, 16bits/20bits/24bit

3. Standard I2S mode, 16bits/20bits/24bit

The CH7036’s Pin 51, Pin 52 and Pin 53 are dedicated for the I

S connection. The I

S decoder can be enabled by

setting “0” to the bit-6 of the offset 1Eh - Register Page 1. In addition, the bit-6 of the Register 07h - Register Page

1 will also need to be switched to “0” to power on the decoder.

MSB LSB MSB LSB MSB

Channel A Channel B

OLRCK

OSCLK

SDOUT

Left

Justified

(Out)

OLRCK

OSCLK

SDOUT

(Out)

MSB LSB MSB LSB MSB

Channel A Channel B

MSB LSB MSB LSB

Channel A Channel B

OLRCK

OSCLK

SDOUT

Right

Justified

(Out)

MSB Extended MSB Extended

Figure 6: I2S interface format

CHRONTEL

CH7036

12 201-1000-009 Rev. 1. 24, 08/15/2011

2.3 DAC Output

2.3.1 Analog RGB Output

The CH7036 has three high speed video DACs for supporting analog RGB outputs. Two additional pins also

provide vertical sync and horizontal sync for driving the analog RGB monitor. A composite sync is available

through programming registers (Table 3). The CH7036 can support analog RGB display resolution up to 1080p.

Table 3: Composite sync type

CSSEL[2:0] Composite sync type

0 Vsync XOR Hsync

1 Vsync OR Hsync

2 Vsync AND Hsync

3 Vsync XOR Hsync 2

4 Vsync XOR Hsync 3

5 Vsync XOR Hsync +

Equalizing pluse 1

6 Vsync XOR Hsync +

Equalizing pluse 2

7 (~Vsync) AND Hsync OR

Vsync

2.3.2 DAC output Configuration

Analog RGB components output can be reassigned to any of the three DACs output pins of the CH7036 through

registers programming. Table 4 below lists the DAC output mappings:

Table 4: Video DAC Configurations for The chip

DACSP[2:0] DAC0 DAC1 DAC2

000 R G B

001 R B G

010 G R B

011 G B R

100 B R G

101 B G R

Each DAC can output R or G or B based on the setting of DACSP[2:0] in the offset 75h[2:0] – Register Page 1;

default value is “000”  DAC0=R, DAC1=G, DAC2=B.

2.3.3 DAC single/double termination

The CH7036’s DAC output can be single terminated (75 Ω) or double terminated (37.5 Ω). Using the single

termination will reduce device’s power consumption while the double termination can improve the performance and

stability. Please refer to the description of the SEL_R bit, which is the bit-5 of the offset 1Ah - Register Page 2.

2.3.4 DAC connection detect

The chip will automatically detect the DAC connection status in every 1 second interval in default mode. To read

back the status of the DAC connection, please refer to [7:2] bits of the offset 7Ch – Register Page 2. If the

CH7036’s VGA output feature has been intentionally disabled by the system manufacture, the detection mechanism

can be switched off by setting the SPPSNS bit to “1” for reducing power dissipation.

2.3.5 Picture enhancement

CHRONTEL

CH7036

201-1000-009 Rev. 1.24, 08/15/2011 13

The horizontal and the vertical positions of the VGA display can be adjusted through offsets 39h, 3Ah and 3Bh -

“0” first; the sharpness of the display text will reflect upon the value in the [2:0] of the offset 2Eh - Register Page 1.

2.4 HDMI/DVI Output

The device’s HDMI/DVI link includes three TMDS Data channels and a single TMDS Clock channel. The TMDS

Clock channel constantly runs at the pixel rate of the transmitted video. During every cycle of the TMDS Clock

channel, each of the three TMDS data channels transmits a 10-bit character. This 10-bit word is encoded using one

of several different coding techniques.

The order of HDMI output pins can be swapped by setting bits[ 4:0], the offset 4Ch – Register Page 1:

Table 5: CH7036 HDMI Output Pins Mapping

HD_LV_SEQ[4:0] DATA0 DATA1 DATA2 CLOCK

0 0 1 2 3

1 0 1 3 2

2 0 2 1 3

3 0 2 3 1

4 0 3 1 2

5 0 3 2 1

6 1 0 2 3

7 1 0 3 2

8 1 2 3 0

9 1 2 0 3

10 1 3 2 0

11 1 3 0 2

12 2 0 1 3

13 2 0 3 1

14 2 1 0 3

15 2 1 3 0

16 2 3 0 1

17 2 3 1 0

18 3 0 1 2

19 3 0 2 1

20 3 1 0 2

21 3 1 2 0

22 3 2 0 1

23 3 2 1 0

In addition, toggling the bit 5 of the same register will invert the polarity of HDMI output’s clock and data. Altering

the HSync and Vsync polarities can be achieved by programming the bit-6 and the bit-5 of the offset 61h – Register

Page 4 accordingly.

2.5 LVDS Output

There are 4 pairs serial data lines (LDC0 through LDC3) and one pair serial clock lines (LLC) in the CH7036’s

LVDS output. The serial data stream on each signal line shall be at a bit rate that is seven times the pixel rate. The

LVDS output supports 18-bit/24-bit (Figure 7,8) single pixel format defined by the SPWG specification.

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