"BQ79616系列汽车级电池监控芯片手册及功能安全规范介绍"

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The BQ79616-Q1, BQ79614-Q1, and BQ79612-Q1 are functional safety-compliant automotive battery monitor, balancer, and integrated hardware protector chips designed for automotive applications. These chips have been qualified for automotive use, meeting AEC-Q100 standards. They are capable of operating within a temperature range of -40°C to 125°C and have been classified for HBM ESD level 2 and CDM ESD level C4B. Developed specifically for functional safety applications, these chips come with documentation to aid in ISO 26262 compliance. This ensures that they meet the stringent requirements for safety-critical systems in automotive environments. The BQ79616-Q1, BQ79614-Q1, and BQ79612-Q1 chips provide a reliable and robust solution for monitoring and protecting automotive batteries, helping to prevent potential hazards and ensure the safe operation of vehicles. With their advanced features and strict compliance with automotive standards, the BQ79616-Q1, BQ79614-Q1, and BQ79612-Q1 chips are ideal for use in electric vehicles, hybrid vehicles, and other automotive applications where battery monitoring and protection are crucial. These chips provide peace of mind for automotive manufacturers and drivers alike, knowing that their batteries are being monitored and protected by high-quality, safety-compliant components.

8.5 Electrical Characteristics (continued)

over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ACC_AUX_GPIO_AB

Accuracy from AUX ADC on GPIO

0.08V<V

<0.2V, 85

C<T

<125

C -6.00 6.00 mV

0.2V<V

<4.6V, -40

C<T

<105

C -6.00 6.00 mV

4.6V<V

<4.8V, -40

C<T

<-20

C -6.00 6.00 mV

ACC_MAIN_BB

Total channel accuracy for (BBP-BBN)

from Main ADC

LPF_BB[2:0] = 0x00 -1.1 1.1 mV

ACC_AUX_BB

Total channel accuracy for (BBP-BBN)

from AUXADC

-4 4 mV

ACC_AUX_BAT

AUX ADC measurement accuracy for

BAT pin

Vbat pack range: 32V to 72V, T

-40

C to 125

-225 135 mV

ACC_AUX_REFL

AUX ADC measurement result 1.092 1.1 1.106 V

ACC_AUX_VBG2

AUX ADC measurement result 1.092 1.1 1.106 V

ACC_AUX_VCM

AUX ADC measurement result 2.400 2.5 2.550 V

ACC_AUX_AVAO_RE

AUX ADC measurement result 2.400 2.47 2.550 V

ACC_AUX_AVDD_RE

AUX ADC measurement result 2.400 2.47 2.550 V

ACC_AUX_OVDAC

AUX ADC measurement result Setting at 4.475V; T

= -20

C to 65

C 4.450 4.500 V

ACC_AUX_OVDAC

AUX ADC measurement result Setting at 4.475V; T

= -40

C to 105

C 4.445 4.500 V

ACC_AUX_OVDAC

AUX ADC measurement result Setting at 4.475V; T

= -40

C to 125

C 4.445 4.500 V

ACC_AUX_OVDAC

AUX ADC measurement result Setting at 3.8V 3.770 3.825 V

ACC_AUX_OVDAC

AUX ADC measurement result Setting at 3V 2.970 3.030 V

ACC_AUX_UVDAC

AUX ADC measurement result Setting at 3.1V 3.095 3.1 3.150 V

ACC_AUX_VCBDONE

DAC

AUX ADC measurement result Setting at 4V 3.950 4 4.050 V

ACC_AUX_OTDAC

AUX ADC measurement result Setting at 39% 1.900 1.95 2.000 V

ACC_AUX_UTDAC

AUX ADC measurement result Setting at 80% 3.950 4 4.050 V

ACC_MAIN_TSREF

Main ADC measurement result 4.975 5 5.025 V

ACC_MAIN__DIETEM

Total channel accuracy for Die Temp1

measurement (+/-)

3 ℃

ACC_AUX_DIETEMP

Total channel accuracy for Die Temp2

measurement (+/-)

6 ℃

Reference Voltages

REFH

REFHP to REFHM voltage 4.975 5 5.025 V

HW Voltage Comparator/Protector (CELL OV/UV)

OV_COMP_RANGE

OV comparator detection

threshold setting range (not accuracy)

Step of 25mV 2700 3000 mV

Step of 25mV 3600 3800 mV

Step of 25mV 4175 4500 mV

OV_COMP_HYS

OV comparator hysteresis after

detection

50 mV

OV_COMP_ACC

OV comparator accuracy

= -20

C to 65

C -24 24 mV

= -40

C to 105

C -28 28 mV

UV_COMP_RANGE

UV comparator detection threshold

setting range (not accuracy)

Step of 50mV 1200 3100 mV

UV_COMP_HYS

UV comparator hysteresis

after detection

50 mV

UV_COMP_ACC

UV comparator accuracy

= -20

C to 65

C -35 35 mV

= -40

C to 105

C -50 50 mV

HW Temperature Comparator/Protector (NTC OT/UT)

TI Confidential - NDA Restrictions

BQ79616-Q1

SLUSE81A – AUGUST 2020 – REVISED DECEMBER 2020

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8.5 Electrical Characteristics (continued)

over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OT_COMP_RANGE

OT comparator

detection threshold setting range (not

accuracy)

Step of 1%, ratiometric with respect to

TSREF

10 39 %

OT_COMP_HYS

OT comparator hysteresis

after detection

2 %

OT_COMP_ACC

OT comparator accuracy -0.5 0.5 %

UT_COMP_RANGE

UT comparator detection threshold

range

Step of 2%, ratiometric with respect to

TSREF

66 80 %

UT_COMP_HYS

UT comparator hysteresis

after detection

2 %

UT_COMP_ACC

UT comparator accuracy -0.5 0.5 %

Digital I/Os (TX, RX, GPIO, SPI master)

Output as logic level high (TX, GPIO

as output)

GPIO is configured as output. I

OUT

1mA

CVDD

-0

Output as logic level low (TX, NFAULT,

GPIO as output)

GPIO is configured as output. I

OUT

1mA

0.3 V

Input as logic level high (RX, GPIO as

fault input)

GPIO is configured as input. I

OUT

1mA

0.75 x

CVDD

Input as logic level low (RX, GPIO as

fault input)

GPIO is configured as input. I

OUT

1mA

0.25 x

CVDD

WK_PU

GPIO weak pull-up resistance 20 37 60 KΩ

WK_PD

GPIO weak pull-down resistance 20 40 60 KΩ

COML and COMH

DCTX

Transmitter output impedance (COML

and COMH)

18 Ω

DCCM

Common mode impedance (COML

and COMH)

45 kΩ

DCCM

Common mode voltage (COML and

COMH)

2.21 2.5 2.76 V

COMM_DATA1

Receiver threshold range (V

COMP

COML

) form communication

CODE:0 0.4 1.2 V

COMM_TONE1

Receiver threshold range (V

COMP

COML

) form Tone

CODE:0 0.4 1.2 V

8.6 Timing Requirements

over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

POWER STATE TIMING

SU(WAKE_SHUT)

Startup from SHUTDOWN to ACTIVE

mode

Base device: From the end of WAKE

ping to the start of a forwading WAKE

tone

6 10 ms

Stack device: From the end of a

recevied WAKE tone to the start of a

forwading WAKE tone

6 10 ms

SU(SLP2ACT)

Startup from SLEEP to ACTIVE mode

(with SLEEP2ACTIVE ping/tone)

Base device: From the end of

SLEEP2ACTIVE ping to the start of

the forwarding SLEEP2ACTIVE tone

230 µs

Stack device: From the end of

SLEEP2ACTIVE tone to the start of

the forwarding SLEEP2ACTIVE tone

230 µs

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BQ79616-Q1

SLUSE81A – AUGUST 2020 – REVISED DECEMBER 2020

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8.6 Timing Requirements (continued)

over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

SU(WAKE_SLP)

Startup from SLEEP to ACTIVE mode

(with WAKE ping/tone)

Base device: From the end of WAKE

ping to the start of a forwading WAKE

tone

1 ms

Stack device: From the end of a

recevied WAKE tone to the start of a

forwading WAKE tone

1 ms

SLP

From ACTIVE to SLEEP mode

From receiving SLEEP entry condition

to enter in SLEEP mode

100 µs

SHTDN

From ACTIVE to SLHUTDOWN mode

From receiving SHUTDOWN entry

condition to enter in SHUTDOWN

mode (all LDOs in 10% of their

norminal value)

20 ms

RST

Reset time during ACTIVE mode

CONTROL1[SOFT_RST] = 1 is sent to

a completion of the digital reset

1 ms

HWRST

The time device will be in HW reset,

after HW reset ping/tone issued

75 ms

SUPPLIES TIMING

TSREF_ON

TSREF ramp up time (10%-90%) C

TSREF

= 1µF 6 ms

TSREF_OFF

TSREF ramp down time (90%-10%) C

TSREF

= 1µF 8 ms

PING SIGNAL TIMING

HLD_WAKE

WAKE ping low time on RX pin; no

external load on CVDD

2 2.5 ms

HLD_SD

SHUTDOWN ping low time on RX pin;

no external load on CVDD

7 10 ms

UART(StA)

SLEEPtoACTIVE ping low time on RX

250 300 µs

HLD_HWRST

HW_RESET ping low time on RX pin 36 ms

COML and COMH (PULSE and TONE TIMING)

PW_DC

COMM: Pulse width of data (half bit

time) for communiction

250 ns

RECLK_DC

COMM: data reclocking delay

per device from COMH to COML or

viceversa

4 5 µs

COMTONE

Time between pulses of comm tones

(HFO based). Comm Tones are

WAKE, SLEEPtoACTIVE,

SHUTDOWN, HWRST tones

11 15 µs

COMMTONE_HI

The HIGH time of each comms pulse

(HFO base)

0.92 1 1.08 µs

COMMTONE_LO

The LOW time of each comms pulse

(HFO base)

0.92 1 1.08 µs

FLTTONE

Time between pulses of FAULT Tone

(LFO based). Applies to FAULT Tone

and HEARTBEAT

11.5 µs

FLTTONE_HI

The HIGH time of each pulse of the

tone couplete

1 µs

FLTTONE_LO

The LOW time of each pulse of the

tone couplete

1 µs

WAKEDET

Number of pulses to detect as a

WAKE tone

60 pulses

WAKE

Number of pulses to transit for a

WAKE tone

90 pulses

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8.6 Timing Requirements (continued)

over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

SHDNDET

Number of pulses to detect as a

SHUTDOWN tone

180 pulses

SHDN

Number of pulses to transit for a

SHUTDOWN tone

270 pulses

SLPtoACTDET

Number of pulses to detect as a

SLEEPtoACTIVE tone

20 pulses

SLPtoACT

Number of pulses to transit for a

SLEEPtoACTIVE tone

30 pulses

HWRSTDET

Number of pulses to detect as a

HW_RESET tone

540 pulses

HWRST

Number of pulses to transit for a

HW_RESET tone

810 pulses

HBDET

HEARTBEAT: Number of pulses to

detect as a valid tone

20 pulses

HEARTBEAT: Number of pulses

to transit for a tone

30 pulses

HB_PERIOD

HEARTBEAT: Period

between HEARTBEAT Burst (from the

beginning of a HEARTBEAT to the

beginning of the next HEARTBEAT)

360 400 440 ms

HB_TIMEOUT

HEARTBEAT: Timeout to

considered as not receving

HEARTBEAT

0.9 1 1.1 s

HB_FAST

HEARTBEAT: If HEARTBEAT

is received within this time, it is

considered receving HEARTBEAT too

fast

200 ms

FTONEDET

FAULT TONE: Number of pulses to

detect as a valid tone

60 pulses

FTONE

FAULT TONE: Number of pulses

to transit for a tone

90 pulses

FTONE_PERIOD

FAULT TONE: Period between

FAULT TONE Burst (from the

beginning of a FAULT TONE to the

beginning of the next

FAULT TONE)

50 ms

FTS_LATENCY

Fault Tone latency in Stack Device

From time a device receive the tone to

the time the same device detects and

generate its fault tone

48 µs

FTB_LATENCY

Fault Tone latency in Base Device

From the time a device receive the

tone to the time the same device

detects and asserts NFAULT

24 µs

MAIN and AUX ADC TIMING

SAR_CONV

Single conversion time (both Main and

AUX ADCs)

8 µs

MAIN_ADC_CYCLE

Single round robin cycle (Main ADC) 192 µs

AUX_ADC_CYCLE

Single round robin cycle (AUX ADC) 192 µs

AFE_SETTLE

Analog front end (Level shifters)

settling time whenever device enter

ACTIVE mode from SLEEP or

SHUTDOWN

4 ms

ADC_ACC

This includes mux round robin, ADC

conversions, and digital filters.

-1.5 1.5 %

BALANCING TIMING

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8.6 Timing Requirements (continued)

over operating -40℃ to 125℃ free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

BAL_ACC

Balancing timer accuracy -5 5 %

HW COMPARATORS/PROTECTORS TIMING

OV_CYCLE

OV round robin cycle 8 ms

UV_CYCLE

UV round robin cycle 8 ms

OVUV_BIST_CYCLE

OV and UV BIST cycle 21.8 23 24.2 ms

OT_CYCLE

OT round robin cycle 4 ms

UT_CYCLE

UT round robin cycle 4 ms

PWR_BIST_CYCLE

Time needed for the power supply

BIST to complete after the power BIST

go command

10.9 11.5 12.1 ms

OTUT_BIST_CYCLE

OT and UT BIST cycle 19 20 21 ms

HW_COMP_ACC

OV,UV,OT,UT comparators

timing accuracy

-5 5 %

I/O TIMING (TX, RX, GPIO, NFAULT)

RISE

Rise Time

CVDD

> MIN V

CVDD

, C

LOAD

= 150pF,

GPIO in output mode

12 ns

FALL

Fall Time (exclude NFAULT)

CVDD

> MIN V

CVDD

, C

LOAD

= 150pF,

GPIO in output mode

7 ns

FALL_NFAULT

Fall Time on NFAULT

CVDD

> MIN V

CVDD

, C

LOAD

= 150pF,

PULLUP

= 10kΩ

100 ns

UART TIMING

UART

BAUD

UART TX/RX Baud Rate 1 Mbps

UART

ERR_BAUD(RX)

UART RX baud rate error -

requirement on the external host

-1 1 %

UART

ERR_BAUD(TX)

UART TX baud rate error -1.5 1.5 %

UART(CLR)

UART Clear low time 15 20

bit

period

UART(RX_HIGH)

After COMM CLEAR, wait this time

before sending new frame

bit

period

OTP NVM TIMING

CRC_CUST

Time to complet a single cycle of CRC

check on the customer OTP space

175 µs

CRC_FACT

Time to complet a single cycle of CRC

check on the factory OTP space

1.6 ms

SPI MASTER TIMING

SCLK

SCLK frequency 450 500 550 kHz

HIGH,

LOW

SCLK duty cycle 50 %

SS(HIGH)

SS HIGH latency time. Time

from register write high to SS pin high

4 µs

SS(LOW)

SS LOW latency time. Time

from register write low to SS pin low

4 µs

SU(MISO)

MISO input data setup time -

requirement for slave device

MISO stable before SCLK transition 100 ns

HD(MISO)

MISO input dat hold time MISO stable after SCLK transition 0 ns

OSCILLATOR

HFO

High frequency oscillator 31.52 32 32.48 MHz

LFO

Low frequency oscillator 248.9 262 275.1 kHz

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