DesignCon2019：电源噪声引起的抖动分析与测量
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"DesignCon2019年论文01_03：电源噪声引起的时钟抖动的模拟与测量相关性研究"
这篇论文是2019年DesignCon大会的一篇技术报告，主要探讨了电源噪声对核心和数字IP块（ Intellectual Property blocks）时钟抖动的影响，并建立了相应的分析方法。电源噪声引起的时钟抖动（Power Supply Noise Induced Jitter，简称PSIJ）是高速电子系统中的关键定时不确定性因素之一。
作者团队，包括来自Intel Corporation的Hyo-Soon Kang、Guang Chen、Ashkan Hashemi、Wern Shin Choo、David Greenhill和Wendem Beyene，他们通过频率依赖的抖动传递函数（Frequency-dependent Jitter Transfer Function）开发了一种分析方法。这种方法可以将电压噪声转化为时钟抖动，从而量化电源噪声对系统性能的影响。
论文中，作者们设计并实现了基于FPGA（Field-Programmable Gate Array）芯片的时钟和数据路径，进行了实际测量，以验证理论分析。他们通过在不同电压下进行延迟测量，验证了频率依赖的抖动传递函数，从而证明了电压变化如何影响时钟抖动。通过集成设备核心操作，产生的电源噪声会诱导出时钟抖动，并对其进行测量。
在研究中，作者们改变噪声频率，观察到频率依赖的抖动与实验测量结果具有相关性。这种相关性的建立，对于理解和改善高速电子系统中的定时精度至关重要，为电源噪声管理和系统设计优化提供了理论依据和实践经验。
这篇论文为理解电源噪声如何影响高速电子系统的性能提供了一个深入的视角，同时提供了有效的分析工具和实验验证，对于提升电子系统的设计质量和可靠性具有重要指导价值。对于从事集成电路设计、信号完整性分析以及电源管理的工程师来说，这些研究成果具有很高的参考价值。
I. Introduction
Power supply noise induced jitter (PSIJ) analysis methodology have been widely
studied for the timing analysis of high-speed serial and parallel interfaces and digital core
timing [1-2]. In the static timing analysis (STA), delay variant due to voltage noise is
applied in the analysis and this approach has pessimism which degrades Fmax severely.
To overcome this pessimism, clock/data path-based jitter transfer function, dynamic noise
modeling and jitter calculation methodologies with consideration of jitter tracking was
proposed [1].
The PSIJ analysis consists of modeling of system-level power distribution network
(PDN), generation of current noise waveforms, and calculation of frequency-dependent
jitter transfer function. To verify the accuracy of the PSIJ methodology, jitter transfer
function correlation between path-based analysis and HSPICE simulation was performed
in [1,3], however, direct measurement correlations of jitters have not been reported as of
yet.
This paper demonstrates simulation and measurement correlation results of PSIJ for
core and digital IP blocks. The overall PSIJ analysis methodology and timing impact to
clock and data paths are described in the next section. For the measurement correlations,
an Intel field-programmable gate array (FPGA) chip is used to design clock and the data
paths [4]. With the integration of core operating circuits in the FPGA design, core noises
with several operating frequencies were generated and modeled taking advantage the
FPGA programmability. By varying the noise frequency, period jitter of clock signal and
the Fmax degradation of data path which are dependent on frequency can be measured
and correlated.
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