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首页2011年JZ4770移动应用处理器数据手册:全新的SoC
2011年JZ4770移动应用处理器数据手册:全新的SoC
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更新于2024-07-31
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JZ4770是一款专为移动应用设计的系统级芯片(SoC),其数据手册于2011年5月27日发布。作为Ingenic半导体有限公司的最新产品,JZ4770集成了多种功能,旨在提供高效能、低功耗的解决方案,适用于便携式电子设备,如智能手机、平板电脑等。 该SoC的主要特点可能包括高性能处理器核心、集成的图形处理单元(GPU)、丰富的外设接口(如USB、Wi-Fi、蓝牙)、以及用于多媒体处理的音频和视频编解码器。JZ4770的数据手册详细列出了其架构、频率、功耗特性、内存选项(如LPDDR2或DDR3支持)以及与操作系统(如Android、RTOS)的兼容性。此外,它还可能提供了电源管理模块,以优化电池续航能力。 版权方面,所有内容受Ingenic Semiconductor Co., Ltd.保护,用户只能根据公司的销售条款和条件使用该文档,不允许进行任何形式的知识产权侵犯。警告用户,文档中的信息是初步的,Ingenic有权在不通知的情况下进行更新。对于医疗或生命维持设备,该SoC并未设计用于此类用途,因此使用时需谨慎。 文档地址位于北京市海淀区中关村软件园8号院西区北洼路东侧的信息中心,Ingenic半导体公司A栋108室。想要获取最新版本和错误修正,请联系Ingenic获取官方资料,以确保设备的最佳性能和合规性。 JZ4770 datasheet是一个关键的技术文档,涵盖了产品的核心特性和使用指南,对开发人员、硬件工程师以及终端产品的制造商来说,它是理解并利用JZ4770功能的关键资源。通过深入研究这份数据手册,用户能够优化产品设计,提升用户体验,并确保遵循制造商的指导,避免潜在的问题和风险。
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Overview
JZ4770 Mobile Application Processor Data Sheet
Copyright © 2005-2011 Ingenic Semiconductor Co., Ltd. All rights reserved.
5
¾ Support data transfer between normal memory (NAND, SRAM, etc. ) / BCH and
system memory (DDR)
– General purpose DMA
¾ 12 independent DMA channels
¾ Support data transfer between On-chip Peripherals (e.g. I2C, MSC, etc.) and
system memory (DDR)
¾ APB bus bridge
– Common features
¾ Descriptor supported
¾ Transfer data units: byte, 2-byte (half word), 4-byte (word), 16-byte, 32-byte or
64-byte
¾ Transfer number of data unit: 1 ~ 224
¾ Independent source and target port width: 8-bit, 16-bit, 32-bit
z The XBurst processor system supports little endian only
1.2.5 AHB Bus Arbiter
– Provide a fair chance for each AHB master to possess the AHB bus
– Fulfill the back-to-back feature of AHB protocol
– Automatic privilege for some masters and programmable privilege for others.
Round-robin possession for masters in the same privilege
1.2.6 System Devices
z Clock generation and power management
– On-chip oscillator circuit for an 32768Hz clock and an 12MHz clock
– On-chip phase-locked loops (PLL) with programmable multiple-ratio. Internal counter are
used to ensure PLL stabilize time
– PLL on/off is programmable by software
– ICLK, PCLK, HCLK, HHCLK, MCLK and LCLK frequency can be changed separately for
software by setting division ratio
– Supports six low-power modes and function: NORMAL mode; DOZE mode; IDLE mode;
SLEEP mode; HIBERNATE mode; and MODULE-STOP function
– Support module power-down
z RTC (Real Time Clock)
– 32-bit second counter
– 1Hz from 32768hz
– Alarm interrupt
– Independent power
– A 32-bits scratch register used to indicate whether power down happens for RTC power
z Interrupt controller
– Total 32 maskable interrupt sources from on-chip peripherals and external request
through GPIO ports
Overview
JZ4770 Mobile Application Processor Data Sheet
Copyright © 2005-2011 Ingenic Semiconductor Co., Ltd. All rights reserved.
6
– Interrupt source and pending registers for software handling
– Unmasked interrupts can wake up the chip in sleep or standby mode
z Timer and counter unit with PWM output and/or input edge counter
– Provide eight separate channels, six of them have input signal transition edge counter
– 16-bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generation when the A counter underflows
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB
Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
– Every channel has PWM output
z OS timer
– One channel
– 32-bit counter and 32-bit compare register
– Support interrupt generation when the counter matches the compare register
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB
Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
z Watchdog timer
– 16-bit counter in RTC clock with 1, 4, 16, 64, 256 and 1024 clock dividing selected
– Generate power-on reset
1.2.7 Audio/Display/UI Interfaces
z LCD controller
– Single-panel display in active mode, and single- or dual-panel displays in passive mode
– 2, 4, 16 grayscales and up to 4096 colors in STN mode
– 2, 4, 16, 256, 4K, 32K, 64K, 256K and 16M colors in TFT mode
– 24-bit data bus
– Support 1,2,4,8 pins STN panel, 16bit, 18bit and 24bit TFT and 8bit I/F TFT
– Display size up to 1920x1080 pixels
– 256×16 bits internal palette RAM
– Support ITU601/656 data format
– Support smart LCD (SRAM-like interface LCD module)
– Support delta RGB
– One single color background and two foreground OSD
– Compressed frame supported
– Support LVDS signal output
z TV encoder
– Support NTSC or PAL
– Support CVBS signal
– 10 bits DAC
z EPD controller
– Supports Electro-Phoretic Display and compatible devices
– Supports different size of display panel
– Supports different width of pixel data
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