1.3 SPI Host Interface
The DW1000 host communications interface is a slave-only SPI. Both clock polarities (SPIPOL=0/1) and phases
(SPIPHA=0/1) are supported. The data transfer protocol supports single and multiple byte read/writes accesses.
All bytes are transferred MSB first and LSB last. A transfer is initiated by asserting SPICSn low and terminated
when SPICSn is deasserted high.
See the DW1000 Datasheet [2] for full details of the SPI interface operation and mode configuration for clock
phase and polarity.
Figure 2: DW1000 SPIPHA=0 Transfer Protocol
1.3.1 SPI Signal Timing
Figure 3: DWM1000 SPI Timing Diagram
Figure 4: DWM1000 SPI Detailed Timing Diagram
Table 2: DWM1000 SPI Timing Parameters
The maximum SPI frequency is 20 MHz when the CLKPLL is locked,
otherwise the maximum SPI frequency is 3 MHz.
SPICSn select asserted low to valid slave output data
SPICLK low to valid slave output data
SPIPOL=0, SPIPHA=0
z MSB 6 5 4 3 2 1 LSB
SPICLK
SPICSn
Cycle
Number, #
SPIMISO
SPIMOSI
SPIPOL=1, SPIPHA=0
SPICLK
z MSB 6 5 4 3 2 1 LSB
1 2 3 4 5 6 7 8
MSB LSB
MSB LSB
9
8*Number of
bytes
X
X
Z
Z