Xilinx Spartan-3 FPGA XC3S1000-4FG1156C技术规格详解

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“xilinx XC3S1000-4FG1156C是Xilinx公司的一款Spartan™-3系列的现场可编程门阵列（FPGA）芯片的手册，包含了该器件的详细介绍、功能描述、电气特性和开关特性等关键信息。” Xilinx的XC3S1000-4FG1156C是一款基于Spartan-3系列的FPGA，它在设计上旨在提供高性能和成本效益的解决方案。以下是对手册中各模块的详细解读： 1. **模块1：介绍和订购信息** - **介绍**：这部分可能包含该芯片的基本信息，如其设计理念、目标应用领域以及相对于其他产品系列的优势。 - **特性**：会列出XC3S1000-4FG1156C的主要功能特点，如逻辑单元数量、I/O口数目、内置存储器容量等。 - **架构概述**：提供芯片内部结构的概览，包括CLB（配置逻辑块）、IOB（输入/输出块）和其他核心组件。 - **产品可用性**：说明产品的上市状态和供货情况。 - **用户I/O图表**：展示芯片的引脚分配和I/O功能。 - **订购信息**：提供了芯片的不同封装选项和购买相关的详细信息。 2. **模块2：功能描述** - **IOB（输入/输出块）**：这部分详细解释了IOB的功能，包括其支持的不同信号标准（如LVCMOS、LVTTL等）和SelectIO技术，允许灵活的I/O配置。 - **CLB（配置逻辑块）**：CLB是FPGA的核心逻辑元件，用于实现用户逻辑。描述了CLB的架构和工作原理。 - **BlockRAM**：详述了集成在芯片中的内存块，可以作为分布式RAM或双端口RAM使用，对于需要嵌入式存储的应用至关重要。 - **专用乘法器**：讨论了XC3S1000-4FG1156C内集成的硬件乘法器，提高了计算效率。 - **数字时钟管理器（DCM）**：DCM模块提供了灵活的时钟管理，包括分频、倍频和相位调整，对系统时钟的稳定性和精度至关重要。 - **时钟网络**：介绍了芯片内的时钟分布机制，确保时钟信号在整个芯片内的同步。 3. **模块3：直流和开关特性** - **直流电气特性**：这部分提供了芯片工作时的电气限制，包括绝对最大额定值、电源电压规格和推荐操作条件。 - **电源电压规格**：列出了为保证正常工作必须满足的电压范围。 - **推荐操作条件**：描述了芯片在正常工作环境下应遵循的温度、电压和电流限制。这些内容对于理解和设计使用XC3S1000-4FG1156C的电路至关重要。手册还可能包含关于配置过程、设计工具支持、功耗分析以及封装和热特性等方面的信息，为设计者提供了全面的技术指导。在设计过程中，正确理解和应用这些规格是确保项目成功的关键。

Spartan-3 1.2V FPGA Family: Functional Description

DS099-2 (v1.2) July 11, 2003 www.xilinx.com 9

Advance Product Specification 1-800-255-7778

4. If none of the standards assigned to the I/Os of the

(interconnected) bank(s) use V

CCO

, tie all associated

CCO

lines to 2.5V.

5. In general, apply 2.5V to V

CCO

Bank 4 from power-on to

the end of configuration. Apply the same voltage to

CCO

Bank 5 during parallel configuration or a

Readback operation. For information on how to

program the FPGA using 3.3V signals and power, see

the 3.3V-Tolerant Configuration Interface section.

If any of the standards assigned to the Inputs of the bank

use V

REF

, then observe the following additional rules:

1. Leave no V

REF

pins unconnected on any bank.

2. Set all V

REF

lines associated with the bank to the same

voltage level.

3. The V

REF

levels used by all standards assigned to the

Inputs of the bank must agree. The Xilinx development

software checks for this. Tables 4 and 6 describe how

different standards use the V

REF

supply.

If none of the standards assigned to the Inputs of a bank

use V

REF

for biasing input switching thresholds, all associ-

ated V

REF

pins function as User I/Os.

Exceptions to Banks Supporting I/O

Standards

Bank 5 of any Spartan-3 device in a VQ100 or TQ144 pack-

age does not support DCI signal standards. In this case,

bank 5 has neither VRN nor VRP pins.

Furthermore, banks 4 and 5 of any Spartan-3 device in a

VQ100 package do not support signal standards using

REF

(see Ta bl e 4 ). In this case, the two banks do not have

any V

REF

pins.

Supply Voltages for the IOBs

Three different supplies power the IOBs:

1. The V

CCO

supplies, one for each of the FPGA’s I/O

banks, power the output drivers, except when using the

GTL and GTLP signal standards. The voltage on the

CCO

pins determines the voltage swing of the output

signal.

2. V

CCINT

is the main power supply for the FPGA’s internal

logic.

3. The V

CCAUX

is an auxiliary source of power, primarily to

optimize the performance of various FPGA functions

such as I/O switching.

The I/Os During Power-On, Configuration, and

User Mode

With no power applied to the FPGA, all I/Os are in a

high-impedance state. The V

CCINT

(1.2V), V

CCAUX

(2.5V),

and V

CCO

supplies may be applied in any order. Before

power-on can finish, V

CCINT

, V

CCO

Bank 4, and V

CCAUX

must have reached their respective minimum recom-

mended operating levels (see Ta bl e 2 in Module 3: DC and

Switching Characteristics). At this time, all I/O drivers

also will be in a high-impedance state. V

CCO

Bank 4,

CCINT

, and V

CCAUX

serve as inputs to the internal

Power-On Reset circuit (POR).

A Low level applied to HSWAP_EN input enables weak

pull-up resistors on User I/Os from power-on throughout

configuration. A High level on HSWAP_EN disables the

pull-up resistors, allowing the I/Os to float. As soon as

power is applied, the FPGA begins initializing its configura-

tion memory. At the same time, the FPGA internally asserts

the Global Set-Reset (GSR), which asynchronously resets

all IOB storage elements to a Low state.

Upon the completion of initialization, INIT_B goes High,

sampling the M0, M1, and M2 inputs to determine the con-

figuration mode. At this point, the configuration data is

loaded into the FPGA. The I/O drivers remain in a

high-impedance state (with or without pull-up resistors, as

determined by the HSWAP_EN input) throughout configura-

tion.

The Global Three State (GTS) net is released during

Start-Up, marking the end of configuration and the begin-

ning of design operation in the User mode. At this point,

those I/Os to which signals have been assigned go active

while all unused I/Os remain in a high-impedance state. The

release of the GSR net, also part of Start-up, leaves the IOB

registers in a Low state by default, unless the loaded design

reverses the polarity of their respective RS inputs.

In User mode, all weak, internal pull-up resistors on the I/Os

are disabled and HSWAP_EN becomes a “don’t care” input.

If it is desirable to have weak pull-up or pull-down resistors

on I/Os carrying signals, the appropriate symbol — e.g.,

PULLUP, PULLDOWN — must be placed at the appropriate

pads in the design. The Bitstream Generator (Bitgen) option

UnusedPin available in the Xilinx development software

determines whether unused I/Os collectively have pull-up

resistors, pull-down resistors, or no resistors in User mode.

Spartan-3 1.2V FPGA Family: Functional Description

10 www.xilinx.com DS099-2 (v1.2) July 11, 2003

1-800-255-7778 Advance Product Specification

CLB Overview

The Configurable Logic Blocks (CLBs) constitute the main

logic resource for implementing synchronous as well as

combinatorial circuits. Each CLB comprises four intercon-

nected slices, as shown in Figure 5. These slices are

grouped in pairs. Each pair is organized as a column with an

independent carry chain.

The nomenclature that the FPGA Editor — part of the Xilinx

development software — uses to designate slices is as fol-

lows: The letter "X" followed by a number identifies columns

of slices. The "X" number counts up in sequence from the

left side of the die to the right. The letter "Y" followed by a

number identifies the position of each slice in a pair as well

as indicating the CLB row. The "Y" number counts slices

starting from the bottom of the die according to the

sequence: 0, 1, 0, 1 (the first CLB row); 2, 3, 2, 3 (the sec-

ond CLB row); etc. Figure 5 shows the CLB located in the

lower left-hand corner of the die. Slices X0Y0 and X0Y1

make up the column-pair on the left where as slices X1Y0

and X1Y1 make up the column-pair on the right. For each

CLB, the term “left-hand” (or SLICEM) is used to indicated

the pair of slices labeled with an even "X" number, such as

X0, and the term “right-hand” (or SLICEL) designates the

pair of slices with an odd "X" number, e.g., X1.

Elements Within a Slice

All four slices have the following elements in common: two

logic function generators, two storage elements, wide-func-

tion multiplexers, carry logic, and arithmetic gates, as

shown in Figure 6. Both the left-hand and right-hand slice

pairs use these elements to provide logic, arithmetic, and

ROM functions. Besides these, the left-hand pair supports

two additional functions: storing data using Distributed RAM

and shifting data with 16-bit registers. Figure 6 is a diagram

of the left-hand slice; therefore, it represents a superset of

the elements and connections to be found in all slices. See

Function Generator, page 12 for more information.

The RAM-based function generator — also known as a

Look-Up Table or LUT — is the main resource for imple-

menting logic functions. Furthermore, the LUTs in each

left-hand slice pair can be configured as Distributed RAM or

a 16-bit shift register. For information on the former, see

XAPP464: Using Look-Up Tables as Distributed RAM in

Spartan-3 FPGAs; for information on the latter, refer to

XAPP465: Using Look-Up Tables as Shift Registers (SRL16)

in Spartan-3 FPGAs. The function generators located in the

upper and lower portions of the slice are referred to as the

"G" and "F", respectively.

The storage element, which is programmable as either a

D-type flip-flop or a level-sensitive latch, provides a means

for synchronizing data to a clock signal, among other uses.

The storage elements in the upper and lower portions of the

slice are called FFY and FFX, respectively.

Wide-function multiplexers effectively combine LUTs in

order to permit more complex logic operations. Each slice

has two of these multiplexers with F5MUX in the lower por-

tion of the slice and FXMUX in the upper portion. Depend-

ing on the slice, FXMUX takes on the name F6MUX,

F7MUX, or F8MUX. For more details on the multiplexers,

see

XAPP466: Using Dedicated Multiplexers in Spartan-3

FPGAs.

Figure 5: Arrangement of Slices within the CLB

DS099-2_05_040703

Interconnect

to Neighbors

Left-Hand SLICEM

(Logic or Distributed RAM

or Shift Register)

Right-Hand SLICEL

(Logic Only)

CIN

SLICE

X0Y1

SLICE

X0Y0

Switch

Matrix

COUT

CLB

COUT

SHIFTOUT

SHIFTIN

CIN

SLICE

X1Y1

SLICE

X1Y0

Spartan-3 1.2V FPGA Family: Functional Description

12 www.xilinx.com DS099-2 (v1.2) July 11, 2003

1-800-255-7778 Advance Product Specification

The carry chain, together with various dedicated arithmetic

logic gates, support fast and efficient implementations of

math operations. The carry chain enters the slice as CIN

and exits as COUT. Five multiplexers control the chain:

CYINIT, CY0F, and CYMUXF in the lower portion as well as

CY0G and CYMUXG in the upper portion. The dedicated

arithmetic logic includes the exclusive-OR gates XORF and

XORG (upper and lower portions of the slice, respectively)

as well as the AND gates GAND and FAND (upper and

lower portions, respectively).

Main Logic Paths

Central to the operation of each slice are two nearly identi-

cal data paths, distinguished using the terms top and bot-

tom. The description that follows uses names associated

with the bottom path. (The top path names appear in paren-

theses.) The basic path originates at an interconnect-switch

matrix outside the CLB. Four lines, F1 through F4 (or G1

through G4 on the upper path), enter the slice and connect

directly to the LUT. Once inside the slice, the lower 4-bit

path passes through a function generator "F" (or "G") that

performs logic operations. The function generator’s Data

output, "D", offers five possible paths:

1. Exit the slice via line "X" (or "Y") and return to

interconnect.

2. Inside the slice, "X" (or "Y") serves as an input to the

DXMUX (DYMUX) which feeds the data input, "D", of

the FFY (FFX) storage element. The "Q" output of the

storage element drives the line XQ (or YQ) which exits

the slice.

3. Control the CYMUXF (or CYMUXG) multiplexer on the

carry chain.

4. With the carry chain, serve as an input to the XORF (or

XORG) exclusive-OR gate that performs arithmetic

operations, producing a result on "X" (or "Y").

5. Drive the multiplexer F5MUX to implement logic

functions wider than four bits. The "D" outputs of both

the F-LUT and G-LUT serve as data inputs to this

multiplexer.

In addition to the main logic paths described above, there

are two bypass paths that enter the slice as BX and BY.

Once inside the FPGA, BX in the bottom half of the slice (or

BY in the top half) can take any of several possible

branches:

1. Bypass both the LUT and the storage element, then exit

the slice as BXOUT (or BYOUT) and return to

interconnect.

2. Bypass the LUT, then pass through a storage element

via the D input before exiting as XQ (or YQ).

3. Control the wide function multiplexer F5MUX (or

F6MUX).

4. Via multiplexers, serve as an input to the carry chain.

5. Drives the DI input of the LUT. See Distributed RAM

section.

6. BY can control the REV inputs of both the FFY and FFX

storage elements. See Storage Element Section.

7. Finally, the DIG_MUX multiplexer can switch BY onto to

the DIG line, which exits the slice.

Other slice signals shown in Figure 6, page 11 are dis-

cussed in the sections that follow.

Function Generator

Each of the two LUTs (F and G) in a slice have four logic

inputs (A1-A4) and a single output (D). This permits any

four-variable Boolean logic operation to be programmed

into them. Furthermore, wide function multiplexers can be

used to effectively combine LUTs within the same CLB or

across different CLBs, making logic functions with still more

input variables possible.

The LUTs in both the right-hand and left-hand slice-pairs

not only support the logic functions described above, but

also can function as ROM that is initialized with data at the

time of configuration.

The LUTs in the left-hand slice-pair (even-numbered col-

umns such as X0 in Figure 5) of each CLB support two

additional functions that the right-hand slice-pair (odd-num-

bered columns such as X1) do not.

First, it is possible to program the “left-hand LUTs” as dis-

tributed RAM. This type of memory affords moderate

amounts of data buffering anywhere along a data path. One

left-hand LUT stores 16 bits. Multiple left-hand LUTs can be

combined in various ways to store larger amounts of data. A

dual port option combines two LUTs so that memory access

is possible from two independent data lines. A Distributed

ROM option permits pre-loading the memory with data dur-

ing FPGA configuration For more information, see the Dis-

tributed RAM section.

Second, it is possible to program each left-hand LUT as a

16-bit shift register. Used in this way, each LUT can delay

serial data anywhere from one to 16 clock cycles. The four

left-hand LUTs of a single CLB can be combined to produce

delays up to 64 clock cycles. The SHIFTIN and SHIFTOUT

lines cascade LUTs to form larger shift registers. It is also

possible to combine shift registers across more than one

CLB. The resulting programmable delays can be used to

balance the timing of data pipelines.

Block RAM Overview

All Spartan-3 devices support block RAM, which is orga-

nized as configurable, synchronous 18Kbit blocks. Block

RAM stores relatively large amounts of data more efficiently

than the distributed RAM feature described earlier. (The lat-

ter is better suited for buffering small amounts of data any-

where along signal paths.) This section describes basic

Block RAM functions. For more information, see

XAPP463:

Using Block RAM in Spartan-3 FPGAs.

Spartan-3 1.2V FPGA Family: Functional Description

DS099-2 (v1.2) July 11, 2003 www.xilinx.com 13

Advance Product Specification 1-800-255-7778

The aspect ratio — i.e., width vs. depth — of each block

RAM is configurable. Furthermore, multiple blocks can be

cascaded to create still wider and/or deeper memories.

A choice among primitives determines whether the block

RAM functions as dual- or single-port memory. A name of

the form RAM16_S[w

]_S[w

] calls out the dual-port primi-

tive, where the integers w

and w

specify the total data

path width at ports w

and w

, respectively. Thus, a

RAM16_S9_S18 is a dual-port RAM with a 9-bit-wide Port A

and an 18-bit-wide Port B. A name of the form RAM16_S[w]

identifies the single-port primitive, where the integer w

specifies the total data path width of the lone port. A

RAM16_S18 is a single-port RAM with an 18-bit-wide port.

Other memory functions — e.g., FIFOs, data path width

conversion, ROM, etc. — are readily available using the

CORE Generator™ system, part of the Xilinx development

software.

Arrangement of RAM Blocks on Die

The XC3S50 has one column of block RAM. The Spartan-3

devices ranging from the XC3S200 to XC3S2000 have two

columns of block RAM. The XC3S4000 and XC3S5000

have four columns. The position of the columns on the die is

shown in Figure 1 in Module 1: Introduction and Ordering

Information. For a given device, the total available RAM

blocks are distributed equally among the columns. Tabl e 8

shows the number of RAM blocks, the data storage capac-

ity, and the number of columns for each device.

The Internal Structure of the Block RAM

The block RAM has a dual port structure. The two identical

data ports called A and B permit independent access to the

common RAM block, which has a maximum capacity of

18,432 bits — or 16,384 bits when no parity lines are used.

Each port has its own dedicated set of data, control and

clock lines for synchronous read and write operations.

There are four basic data paths, as shown in Figure 7: (1)

write to and read from Port A, (2) write to and read from Port

B, (3) data transfer from Port A to Port B, and (4) data trans-

fer from Port B to Port A.

Block RAM Port Signal Definitions

Representations of the dual-port primitive

RAM16_S[w

]_S[w

] and the single-port primitive

RAM16_S[w] with their associated signals are shown in

Figure 8a and Figure 8b, respectively. These signals are

defined in Tab l e 9.

Table 8: Number of RAM Blocks by Device

Device

Total Number

of RAM Blocks

Total

Addressable

Locations (bits)

Number

Columns

XC3S50 4 73,728 1

XC3S200 12 221,184 2

XC3S400 16 294,912 2

XC3S1000 24 442,368 2

XC3S1500 32 589,824 2

XC3S2000 40 737,280 2

XC3S4000 96 1,769,472 4

XC3S5000 104 1,916,928 4

Figure 7: Block RAM Data Paths

DS099-2_12_030703

Spartan-3

Dual Port

Block RAM

Read

Write

Read

Write

Read

Port A

Port B

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Xilinx Spartan-3 FPGA XC3S1000-4FG1156C技术规格详解

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