2M字节低功耗Atemel DataFlash AT45DB161B：SPI接口、绿色存储解决方案

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AT45DB161B是一款专为各种数字应用设计的高性能、低功耗Atemel DataFlash存储芯片，它具备2M字节（16兆比特）的存储容量。这款芯片支持单个2.5V至3.6V或2.7V的电源输入，确保了其在宽电压范围内的稳定工作，适合对电源兼容性有较高要求的应用场景。它的接口采用串行外围接口（SPI），允许在高达20MHz的时钟频率下进行数据传输，这大大提高了数据传输的效率。AT45DB161B支持页编程操作，包括单周期擦除和编程，每块内存包含4096页，每页大小为528字节，非常适合于高效的数据存储和更新。为了优化数据处理，芯片内置两个528字节的静态随机存取存储器（SRAM）数据缓冲区，可以在程序非易失性内存的同时接收数据，极大地增强了数据处理能力。此外，该芯片还具备连续读取功能，使得代码复制（code shadowing）应用得以简化。在功耗方面，AT45DB161B表现优秀，典型情况下，活跃读取电流仅为4毫安，而在待机模式下，仅有2微安的超低静态电流，有助于延长电池寿命，特别适合对低功耗有严格要求的设备。硬件数据保护功能是另一个重要特性，它提供了额外的安全保障，确保数据的完整性。AT45DB161B完全兼容之前的AT45DB161版本，且所有输入引脚，如SI（串行输入）、SCK（时钟）、CS（片选）、RESET（复位）和WPP（写保护）都具有5.0V的耐受性，适应不同的电路环境。温度范围广泛，无论是商业级还是工业级应用，都能在-40℃到+85℃的极端条件下正常工作。同时，考虑到环保需求，AT45DB161B提供绿色包装选项，不含铅和卤化物，符合现代电子产品的环保标准。 AT45DB161B凭借其高性能、低功耗、兼容性强和广泛的温度适应性，成为嵌入式系统和物联网应用中的理想选择，无论是用于存储音频、图像、程序代码还是各类数据，都能高效地满足需求。

AT45DB161B

2224I–DFLSH–10/04

BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A

previously erased page within main memory can be programmed with the contents of

either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or

89H for buffer 2, must be followed by the two reserved bits, 12 address bits

(PA11 - PA0) that specify the page in the main memory to be written, and ten additional

don’t care bits. When a low-to-high transition occurs on the CS

pin, the part will program

the data stored in the buffer into the specified page in the main memory. It is necessary

that the page in main memory that is being programmed has been previously erased.

The programming of the page is internally self-timed and should take place in a maxi-

mum time of t

. During this time, the status register will indicate that the part is busy.

Successive page programming operations without doing a page erase are not recom-

mended. In other words, changing bytes within a page from a “1” to a “0” during multiple

page programming operations without erasing that page is not recommended.

PAGE ERASE: The optional Page Erase command can be used to individually erase

any page in the main memory array allowing the Buffer to Main Memory Page Program

without Built-in Erase command to be utilized at a later time. To perform a Page Erase,

an opcode of 81H must be loaded into the device, followed by two reserved bits,

12 address bits (PA11 - PA0), and ten don’t care bits. The 12 address bits are used to

specify which page of the memory array is to be erased. When a low-to-high transition

occurs on the CS

pin, the part will erase the selected page to 1s. The erase operation is

internally self-timed and should take place in a maximum time of t

. During this time,

the status register will indicate that the part is busy.

BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer

to Main Memory Page Program without Built-in Erase command to be utilized to reduce

programming times when writing large amounts of data to the device. To perform a

Block Erase, an opcode of 50H must be loaded into the device, followed by two

reserved bits, nine address bits (PA11 - PA3), and 13 don’t care bits. The nine address

bits are used to specify which block of eight pages is to be erased. When a low-to-high

transition occurs on the CS

pin, the part will erase the selected block of eight pages to

1s. The erase operation is internally self-timed and should take place in a maximum

time of t

. During this time, the status register will indicate that the part is busy.

Block Erase Addressing

PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block

000000000XXX0

000000001XXX1

000000010XXX2

000000011XXX3

•

111111100XXX508

111111101XXX509

111111110XXX510

111111111XXX511

AT45DB161B

2224I–DFLSH–10/04

MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combina-

tion of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase

operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then pro-

grammed into a specified page in the main memory. To initiate the operation, an 8-bit

opcode, 82H for buffer 1 or 85H for buffer 2, must be followed by the two reserved bits

and 22 address bits. The 12 most significant address bits (PA11 - PA0) select the page

in the main memory where data is to be written, and the next ten address bits

(BFA9 - BFA0) select the first byte in the buffer to be written. After all address bits are

shifted in, the part will take data from the SI pin and store it in one of the data buffers. If

the end of the buffer is reached, the device will wrap around back to the beginning of the

buffer. When there is a low-to-high transition on the CS

pin, the part will first erase the

selected page in main memory to all 1s and then program the data stored in the buffer

into the specified page in the main memory. Both the erase and the programming of the

page are internally self-timed and should take place in a maximum of time t

. During

this time, the status register will indicate that the part is busy.

Additional Commands MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred

from the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bit

opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the two reserved bits,

12 address bits (PA11 - PA0) which specify the page in main memory that is to be trans-

ferred, and ten don’t care bits. The CS

pin must be low while toggling the SCK pin to

load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of

the page of data from the main memory to the buffer will begin when the CS

pin transi-

tions from a low to a high state. During the transfer of a page of data (t

XFR

), the status

MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can

be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode,

60H for buffer 1 and 61H for buffer 2, must be followed by 24 address bits consisting of

the two reserved bits, 12 address bits (PA11 - PA0) which specify the page in the main

memory that is to be compared to the buffer, and ten don’t care bits. The CS

pin must be

low while toggling the SCK pin to load the opcode, the address bits, and the don’t care

bits from the SI pin. On the low-to-high transition of the CS

pin, the 528 bytes in the

selected main memory page will be compared with the 528 bytes in buffer 1 or buffer 2.

During this time (t

XFR

), the status register will indicate that the part is busy. On comple-

tion of the compare operation, bit 6 of the status register is updated with the result of the

compare.

AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or

multiple pages of data are modified in a random fashion. This mode is a combination of

two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page

Program with Built-in Erase. A page of data is first transferred from the main memory to

buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed

back into its original page of main memory. To start the rewrite operation, an 8-bit

opcode, 58H for buffer 1 or 59H for buffer 2, must be followed by the two reserved bits,

12 address bits (PA11 - PA0) that specify the page in main memory to be rewritten, and

ten additional don’t care bits. When a low-to-high transition occurs on the CS

pin, the

part will first transfer data from the page in main memory to a buffer and then program

the data from the buffer back into same page of main memory. The operation is inter-

nally self-timed and should take place in a maximum time of t

. During this time, the

status register will indicate that the part is busy.

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