AMBA 2.0规范：AHB总线协议详解

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AMBA 2.0 Specification 是一个高级微控制器总线架构 (Advanced Microcontroller Bus Architecture, AMBA) 的详细规范文档，由 Advanced RISC Machines Ltd (ARM) 发布，日期为1997年4月。这个文档的官方编号为 ARMIHI0001D，它为用户提供了关于如何设计、实现和操作基于 AMBA 2.0 架构的系统的关键信息。 AMBA 是一种开放的标准，旨在简化嵌入式处理器之间的通信，特别是针对那些需要高性能和低能耗的应用，如移动设备、消费电子和工业控制等。AMBA 2.0 版本在前一代的基础上进行了改进，增强了兼容性和功能，包括： 1. 高性能数据总线：AMBA 2.0 提供了高速、低延迟的总线接口，支持多种数据宽度，如 AHB (Advanced High-performance Bus)，这是一种全速、全双工总线，能够支持多个主设备连接，并支持突发传输，提高了系统性能。 2. 多级缓存支持：该规范允许通过缓存一致性协议实现不同层次的缓存协调，确保数据的一致性，这对于提高系统响应速度至关重要。 3. 模块化设计：AMBA 2.0 允许灵活的模块化设计，使得硬件设计师可以根据具体应用需求选择和组合不同的接口，如AHB、APB (Advanced Peripheral Bus) 或其他定制化的总线。 4. 电源管理：为了适应低功耗环境，AMBA 2.0 强调了电源管理和时钟管理，支持动态调整性能以适应不同的功耗需求。 5. 知识产权保护：文档中强调了所有知识产权的保留，指出未经版权持有者书面许可，不得擅自复制或修改文档中的信息或产品描述。此外，还规定了产品可能不断进行开发和改进，因此提供的规格可能会有所变动。 6. 免责声明：尽管 ARM 以良好信仰提供信息，但该文档不构成任何形式的保证，包括但不限于适销性或特定用途的适合性。使用文档中的信息或产品时，用户需自行承担风险，ARM 不对由此产生的任何损失或损害负责。 AMBA 2.0 Specification 是嵌入式系统设计者的重要参考资料，它为构建高效、灵活和可扩展的系统提供了标准化的接口和策略。对于从事此类设计或想要深入了解该技术的工程师而言，理解和遵循这个规范是至关重要的。

Functional Description

3-4 AMBA Specification

ARM IHI 0001D

3.2.2 ASB Components

An ASB system design contains the following components:

ASB Master - A bus master is able to initiate read and write operations by providing

an address and control information. Only one bus master is allowed to actively use the

bus at any one time.

The system may contain one or more bus masters, typically a system would contain at

least the processor and test interface, however it would also be common for a DMA

(Direct Memory Access) or DSP (Digital Signal Processor) to be included as bus

masters.

ASB Slave - A bus slave responds to a read or write operation within a given

address-space range. The bus slave signals back to the active master the success,

failure or waiting of the data transfer.

The external memory interface, APB bridge and any internal memory are the most

common ASB slaves. Any other peripheral in the system could also be included as an

ASB slave, however low bandwidth peripherals typically reside on the APB.

ASB Decoder - The bus decoder performs the decoding of the transfer addresses

and selects slaves appropriately. The bus decoder also ensures that the bus remains

operational when no bus transfers are required.

A single centralised decoder is required in all ASB implementations.

ASB Arbiter - The bus arbiter ensures that only one bus master at a time is allowed

to initiate data transfers. The arbitration scheme is not enforced such that 'highest

priority' or 'fair' access algorithms may be implemented depending on the application

requirements.

An ASB would include only one arbiter, although this is would be trivial in single bus

master systems.

3.2.3 APB Components

An APB implementation would contain the following components:

APB Bridge - A single bridge is required to convert ASB transfers into a suitable

format for the slave devices on the APB. The bridge provides latching of all address,

data and control signals, as well as providing a second level of decoding to generate

slave select signals for the APB peripherals.

APB Slave - The APB can contain many different APB slaves.

The APB slaves have the following interface specification:

• Address and control valid throughout the access (unpipelined).

• Zero-power interface during non-peripheral bus activity (peripheral bus is static

when not in use).

• Timing provided by decode with strobe timing (unclocked interface).

• Write data valid for the whole access (allowing glitch-free transparent latch

implementations).

Functional Description

3-8 AMBA Specification

ARM IHI 0001D

The address and control signals start to change in the BCLK HIGH phase before the

transfer starts, but for a Non-sequential transfer a valid address may not be available

until very late in the BCLK HIGH phase, or even until the start of the clock LOW

phase at the beginning of the transfer.

The decoder, which requires a stable address in order to select the correct slave, will

automatically insert a wait state in the first cycle of Non-sequential transfers. This is

referred to as a 'Decode Cycle' and provides an adequate time for the decoder to

examine the high order address lines and assert the appropriate DSELx during the

HIGH phase of the decode cycle.

For the remaining cycles of the transfer, the slave will provide a transfer response and

the data exchange will occur between the master and slave.

Note: In certain system designs, which are typically those with a low frequency

system clock, the address is valid early enough in the BCLK HIGH phase before

the start of the transfer, allowing the decoder to generate a valid DSELx signal

before the falling edge of BCLK.

Such systems do not require the addition of a decode cycle at the start of the

Non-sequential transfers and the operation of such a system is described in more

detail in section 3.5, “Address Decode”.

The data bus, BD[31:0], must be valid by the falling edge of BCLK at the end of the

transfer. During a write cycle, the bus master is responsible for driving the data bus,

which it will do from the start of the clock HIGH phase, in order that the slave may

accept valid data by the falling edge of the clock. During a read cycle the appropriate

slave must drive the data bus, such that it is valid by the end of the HIGH phase.

Because a number of different bus slaves may drive data on to the ASB it is necessary

to ensure that different slaves do not overlap when driving data onto the bus. An

entire phase of non-overlap is provided as slaves/masters may not drive data during

the clock LOW phase at the start of a Non-sequential transfer.

As many of the bus signals are shared and have turnaround periods when there is no

active driver, it is necessary to ensure that bus hold cells are provided to prevent

floating levels being present on the bus.

3.4.2 Sequential Transfer

A Sequential transfer occurs when the address is related to that of the previous

transfer. The control information, as indicated by BWRITE, BPROT and BSIZE, will

be the same as the previous transfer.

If the Sequential transfer follows a Non-sequential or another Sequential transfer, the

address can be calculated by using the previous size and address. For example a

burst of word accesses would be to addresses A, A+4, A+8, whereas a burst of

halfword accesses would be to addresses A, A + 2, A + 4.

If a Sequential transfer follows an Address-only cycle then the address will be the

same as that of the Address-only cycle. This combination of an Address-only followed

by Sequential allows both a single access using a Sequential transfer and also allows

a burst of transfers to start with a Sequential transfer. An example of the use of an

Address-only followed by Sequential of is shown later in Figure 3-6.

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