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TC358870XBG
16 2015-02-02
Table of Figures
Figure 1.1 TC358870XBG System Overview .......................................................................................... 21
Figure 2.1 TC358870XBG 80-Pin Layout (Top View).............................................................................. 24
Figure 3.1 Block Diagram of TC358870XBG ........................................................................................... 25
Figure 3.2 Line Splitting for Dual DSI Link ............................................................................................... 28
Figure 3.3 Line Overlap Splitting in Dual DSI Link ................................................................................... 29
Figure 3.4 DSI Command Transmission Timing ...................................................................................... 30
Figure 3.5 DSI Short Command Packet Assembly .................................................................................. 31
Figure 3.6 DSI Long Command Packet Assembly .................................................................................. 32
Figure 3.7 Flow diagram for LPRX data reception using Register interface ........................................... 34
Figure 3.8 CEC reception overview ......................................................................................................... 35
Figure 3.9 CEC noise cancellation example ............................................................................................ 36
Figure 3.10 CEC start bit detection .......................................................................................................... 36
Figure 3.11 waveform error detection ...................................................................................................... 37
Figure 3.12 sampling time example ......................................................................................................... 37
Figure 3.13 CEC transmission example .................................................................................................. 38
Figure 3.14 Transmission starts ............................................................................................................... 38
Figure 3.15 Transmission timing .............................................................................................................. 39
Figure 3.16 Arbitration Error check .......................................................................................................... 39
Figure 3.17 CEC Block diagram............................................................................................................... 40
Figure 3.18 Data input timing of standard format (Sony format); L_ch=H, R_ch=L ................................ 42
Figure 3.19 Data input timing of Left-Justified format; L_ch=H, R_ch=L................................................. 42
Figure 3.20 Data input timing of I2S data format (Phillips format); L_ch=L, R_ch=H ............................. 43
Figure 3.21 HBR Audio stream over 1 I2S lane and four (4) I2S lanes ................................................... 44
Figure 3.22 I2S N-Channel TDM timing ................................................................................................... 45
Figure 3.23 NEC Configuration of Frame ................................................................................................ 46
Figure 3.24 NEC Bit Description .............................................................................................................. 46
Figure 3.25 NEC Frame Interval (Tf) ....................................................................................................... 46
Figure 3.26 Example of Lead Code min/max values for H and L detection ............................................ 47
Figure 3.27 Register Write Transfer over I
2
C Bus ................................................................................... 49
Figure 3.28 Random Register Read Transfer over I
2
C Bus .................................................................... 49
Figure 3.29 Continuous Register Read Transfer over I
2
C Bus ................................................................ 49
Figure 3.30 I
2
C Write Transfers Translated to Register Write Accesses ................................................ 50
Figure 3.31 I
2
C Read Transfers to Register Read Accesses .................................................................. 50
Figure 4.1 Power On Sequence ............................................................................................................... 54
Figure 4.2 Power Down Sequence .......................................................................................................... 55
Figure 6.1 TC358870XBG package (P-VFBGA80-0707-0.65-001) ...................................................... 294
Figure 9.1 D-PHY Signaling Levels .................................................................................................... 299
Figure 9.2 Input Glitch Rejection of Low-Power Receivers ................................................................... 302
Figure 9.3 Data to clock timing reference .............................................................................................. 302
Figure 9.4 I2S/TDM Timing Diagram ..................................................................................................... 303
Figure 10.1 Example of DDC I/F Connection ........................................................................................ 305
Figure 10.2 Connection of REXT resistance ......................................................................................... 306
Figure 10.3 Audio Clock External LPF circuit block diagram ................................................................. 306
Figure 10.4 Recommended power supply circuit with external switch .................................................. 307
Figure 10.5 Recommended power supply circuit with current protection regulator .............................. 308
Figure 10.6 Recommended power supply circuit at VDDIO18 = 3.3V .................................................. 309