TC358870XBG HDMI转MIPI DSI桥接芯片详细规格

需积分: 25 45 浏览量更新于2024-07-19 1 收藏 7.29MB PDF 举报

"TC358870XBG 是一款由东芝公司生产的高性能HDMI转MIPI DSI桥接芯片，适用于需要在HDMI输入和MIPI DSI输出之间进行转换的移动设备开发。它能够处理高分辨率（超过4Gbps）的HDMI视频流，并将其转化为MIPI DSI Tx视频信号。与前代产品TC358779XBG相比，TC358870XBG去除了标量功能，但仍能支持最高达7.2Gbps的视频数据传输。这款芯片是为当前及下一代应用处理器设计的，可以利用其HDMI Tx输出端口驱动DSI链接显示。" TC358870XBG的主要特性包括： 1. HDMI-RX接口：兼容HDMI 1.4b标准，可支持多种视频格式，最高可达4K×2K/30fps，最大24位每像素（bps）无深色支持。支持的视频格式有RGB、YCbCr444和YCbCr422，均为24-bpp。 2. 颜色转换：芯片内置了丰富的颜色空间转换功能，包括4:2:2到4:4:4、4:4:4到4:2:2、RGB888到YCbCr以及YCbCr到RGB888/666的转换。 3. 最高HDMI时钟速度：297MHz，确保了高速视频数据的稳定传输。 4. 音频支持：内置音频PLL，支持多种音频格式，提供高质量的音频输出。 5. MIPI DSI Tx：要求双链路MIPIDSITx，1Gbps/数据通道，满足7.2Gbps的视频数据传输需求。 6. 应用场景：适合于需要将HDMI输入转换为MIPI DSI输出的移动设备，如智能手机、平板电脑等，用于驱动高分辨率的显示屏。 7. 设计优势：由于省去了标量功能，TC358870XBG简化了系统设计，降低了功耗，同时保持了强大的视频处理能力。 TC358870XBG是一款针对高清视频流转换优化的芯片，能够有效地连接和转换不同接口的视频信号，为现代移动设备提供灵活的显示解决方案。其高效的颜色转换和音频处理能力，以及对高分辨率视频的支持，使其成为移动设备开发中不可或缺的一部分。

TC358870XBG

16 2015-02-02

Table of Figures

Figure 1.1 TC358870XBG System Overview .......................................................................................... 21

Figure 2.1 TC358870XBG 80-Pin Layout (Top View).............................................................................. 24

Figure 3.1 Block Diagram of TC358870XBG ........................................................................................... 25

Figure 3.2 Line Splitting for Dual DSI Link ............................................................................................... 28

Figure 3.3 Line Overlap Splitting in Dual DSI Link ................................................................................... 29

Figure 3.4 DSI Command Transmission Timing ...................................................................................... 30

Figure 3.5 DSI Short Command Packet Assembly .................................................................................. 31

Figure 3.6 DSI Long Command Packet Assembly .................................................................................. 32

Figure 3.7 Flow diagram for LPRX data reception using Register interface ........................................... 34

Figure 3.8 CEC reception overview ......................................................................................................... 35

Figure 3.9 CEC noise cancellation example ............................................................................................ 36

Figure 3.10 CEC start bit detection .......................................................................................................... 36

Figure 3.11 waveform error detection ...................................................................................................... 37

Figure 3.12 sampling time example ......................................................................................................... 37

Figure 3.13 CEC transmission example .................................................................................................. 38

Figure 3.14 Transmission starts ............................................................................................................... 38

Figure 3.15 Transmission timing .............................................................................................................. 39

Figure 3.16 Arbitration Error check .......................................................................................................... 39

Figure 3.17 CEC Block diagram............................................................................................................... 40

Figure 3.18 Data input timing of standard format (Sony format); L_ch=H, R_ch=L ................................ 42

Figure 3.19 Data input timing of Left-Justified format; L_ch=H, R_ch=L................................................. 42

Figure 3.20 Data input timing of I2S data format (Phillips format); L_ch=L, R_ch=H ............................. 43

Figure 3.21 HBR Audio stream over 1 I2S lane and four (4) I2S lanes ................................................... 44

Figure 3.22 I2S N-Channel TDM timing ................................................................................................... 45

Figure 3.23 NEC Configuration of Frame ................................................................................................ 46

Figure 3.24 NEC Bit Description .............................................................................................................. 46

Figure 3.25 NEC Frame Interval (Tf) ....................................................................................................... 46

Figure 3.26 Example of Lead Code min/max values for H and L detection ............................................ 47

Figure 3.27 Register Write Transfer over I

C Bus ................................................................................... 49

Figure 3.28 Random Register Read Transfer over I

C Bus .................................................................... 49

Figure 3.29 Continuous Register Read Transfer over I

C Bus ................................................................ 49

Figure 3.30 I

C Write Transfers Translated to Register Write Accesses ................................................ 50

Figure 3.31 I

C Read Transfers to Register Read Accesses .................................................................. 50

Figure 4.1 Power On Sequence ............................................................................................................... 54

Figure 4.2 Power Down Sequence .......................................................................................................... 55

Figure 6.1 TC358870XBG package (P-VFBGA80-0707-0.65-001) ...................................................... 294

Figure 9.1 D-PHY Signaling Levels .................................................................................................... 299

Figure 9.2 Input Glitch Rejection of Low-Power Receivers ................................................................... 302

Figure 9.3 Data to clock timing reference .............................................................................................. 302

Figure 9.4 I2S/TDM Timing Diagram ..................................................................................................... 303

Figure 10.1 Example of DDC I/F Connection ........................................................................................ 305

Figure 10.2 Connection of REXT resistance ......................................................................................... 306

Figure 10.3 Audio Clock External LPF circuit block diagram ................................................................. 306

Figure 10.4 Recommended power supply circuit with external switch .................................................. 307

Figure 10.5 Recommended power supply circuit with current protection regulator .............................. 308

Figure 10.6 Recommended power supply circuit at VDDIO18 = 3.3V .................................................. 309

TC358870XBG

17 2015-02-02

List of Tables

Table 2.1 TC358870XBG Functional Signal List ..................................................................................... 22

Table 2.2 BGA80 Pin Count Summary .................................................................................................... 24

Table 3.1 HDMI 3D Structure ................................................................................................................... 26

Table 3.2 InfoFrame Data Registers Summary ....................................................................................... 27

Table 4.1 Possible DSITX0/1_PLL parameters ....................................................................................... 53

Table 4.2 Power On Sequence Timing .................................................................................................... 54

Table 4.3 Power Down Sequence Timing................................................................................................ 55

Table 5.1 Global Register Map ................................................................................................................ 56

Table 5.2 CEC Enable Register ............................................................................................................. 136

Table 5.3 CEC Logical Address Register .............................................................................................. 137

Table 5.4 CEC Reset Register ............................................................................................................... 137

Table 5.5 CEC Receive Enable Register ............................................................................................... 138

Table 5.6 CEC Receive Control Register 1 ........................................................................................... 138

Table 5.7 CEC Receive Control Register 2 ........................................................................................... 140

Table 5.8 CEC Receive Control Register 3 ........................................................................................... 141

Table 5.9 CEC Transmit Enable Register .............................................................................................. 142

Table 5.10 CEC Transmit Control Register ........................................................................................... 143

Table 5.11 CEC Receive Interrupt Status Register ............................................................................... 144

Table 5.12 Interrupt Flag Register ......................................................................................................... 144

Table 5.13 CEC Receive Buffer Registers (01-16) ................................................................................ 145

Table 5.14 CEC Transmit Buffer Registers (01-16) ............................................................................... 145

Table 5.15 Interrupt Flag Register ......................................................................................................... 145

Table 5.16 CEC Interrupt Enable Register ............................................................................................ 146

Table 5.17 CEC Interrupt Enable Register ............................................................................................ 146

Table 6.1 Mechanical Dimension ........................................................................................................... 294

Table 11.1 Revision History ................................................................................................................... 310

TC358870XBG

19 2015-02-02

1 NOTICE OF DISCLAIMER

2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled

3 by any of the authors or developers of this material or MIPI. The material contained herein is provided on

4 an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS

5 AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all

6 other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if

7 any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of

8 accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of

9 negligence.

10 All materials contained herein are protected by copyright laws, and may not be reproduced, republished,

11 distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express

12 prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related

13 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and

14 cannot be used without its express prior written permission.

15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET

16 POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD

17 TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY

18 AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR

19 MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE

20 GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,

21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER

22 CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR

23 ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,

24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH

25 DAMAGES.

26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is

27 further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the

28 contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;

29 and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance

30 with the contents of this Document. The use or implementation of the contents of this Document may

31 involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,

32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI

33 does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any

34 IPR or claims of IPR as respects the contents of this Document or otherwise.

35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:

36 MIPI Alliance, Inc.

37 c/o IEEE-ISTO

38 445 Hoes Lane

39 Piscataway, NJ 08854

40 Attn: Board Secretary

剩余310页未读，继续阅读

xxplg

粉丝: 2
资源: 6

TC358870XBG HDMI转MIPI DSI桥接芯片详细规格

tc358870xbg相关寄存器配置及数据手册

tc358840+70全部最新资料

TC358870各个工作模式驱动配置

TC358870XBG HDMI to DSI Bridge芯片详解

TC358870XBG：超高清到DSI桥接芯片功能规格

TC358870XBG：HDMI到MIPI转换桥接芯片

TC358870XBG：超高速HDMI桥接器开发指南

tc358870xbg 软件

tc358870xbg_hdmi-dsi_tv12p

TC358743XBG：HDMI转MIPI CSI参考设计

最新资源