SIGMADSP ADAU1451/1452: 高性能汽车音频处理器与特性概览

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标题：AD AU1451/1452/1450：一款高性能数字音频处理器描述概述：AD AU1451/1452/1450是一款专为汽车应用设计的新型数字信号处理器(DSP)，它以其卓越的音频处理能力、可编程性以及丰富的特性在音频系统中占据重要地位。该芯片集成了先进的Sigma DSP核心，能够运行高达294.912 MHz的速度，采用1.2 V电压，提供强大的计算性能，每样本支持多达6144个SIMD指令，这对于音频信号的复杂处理非常关键。特色亮点： 1. **音频增强功能**：通过专用的图形编程工具Sigma Studio，开发人员可以轻松定制独特的信号流程，实现音质的优化和提升。 2. **高速性能**：32位Sigma DSP核心，时钟频率高达1.2 V，确保了在48 kHz采样率下高效的数据处理能力。 3. **内存容量**：内置多达40 k words的参数和数据RAM，为复杂的算法提供了足够的存储空间。 4. **延迟池**：支持高达800 ms的数字音频延迟池，有助于实现无缝音频播放和回放效果。 5. **音频接口**：4个串行输入和输出端口，支持48通道32位数字I/O，兼容TDM、I2S、左/右对齐格式以及PCM，灵活性极高。 6. **高级音频源转换**：支持多达8路的立体声ASRC，可实现1:8到7.75:1的采样比率转换，且具有惊人的139 dB DNR，保证了音频质量的高标准。 7. **音频接口扩展**：包含S/PDIF输入输出（仅限于ADAU1452），以及四个PDM麦克风输入通道，满足多路音频输入需求。 8. **多通道TDM**：支持字节寻址的多通道TDM串行端口，便于高效的通信和同步。 9. **时钟管理**：内置时钟振荡器和灵活的时钟发生器，确保精确的时间基准。 10. **温度监控**：集成低功耗温度传感器，用于环境适应和系统稳定性监控。 11. **控制接口**：支持I2C和SPI通信，作为从属或主设备，便于外部接口和配置。 12. **自启动能力**：支持从串行EEPROM的自我引导，简化系统启动流程。 13. **辅助控制**：配备6通道10位SAR辅助控制系统，进一步扩展功能应用范围。 AD AU1451/1452/1450凭借其全面的功能和高度的灵活性，适用于汽车音响、车载娱乐系统、音频解码与编码等领域的高端应用，为实现高质量的音频体验提供了强大的硬件平台。

ADAU1452/ADAU1451/ADAU1450 Data Sheet

PDM Inputs

= −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%. PDM data is latched on both edges of the clock (see

Figure 11).

Table 16.

Parameter t

MIN

MAX

Unit Description

Timing Requirements

SETUP

10 ns Data setup time

HOLD

5 ns Data hold time

HOLD

SETUP

PDM_CLK

PDM_DAT

11486-011

Figure 11. PDM Timing Diagram

Rev. C | Page 16 of 180

Data Sheet ADAU1452/ADAU1451/ADAU1450

ABSOLUTE MAXIMUM RATINGS

Table 17.

Parameter Rating

DVDD to Ground 0 V to 1.4 V

AVDD to Ground

0 V to 4.0 V

IOVDD to Ground 0 V to 4.0 V

PVDD to Ground 0 V to 4.0 V

Digital Inputs DGND − 0.3 V to

IOVDD + 0.3 V

Maximum Ambient Temperature Range −40°C to +105°C

Maximum Junction Temperature

125°C

Storage Temperature Range −65°C to +150°C

Soldering (10 sec) 300°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL CHARACTERISTICS

represents the junction-to-ambient thermal resistance; θ

represents the junction-to-case thermal resistance. All charac-

teristics are for a 4-layer JEDEC board. The exposed pad has

49 vias that are arranged in a 7 × 7 grid.

Table 18. Thermal Resistance

Package Type θ

Unit

72-Lead LFCSP 23.38 3.3 °C/W

MAXIMUM POWER DISSIPATION

The characteristics listed in Table 19 show the absolute worst

case power dissipation for the ADAU1452, ADAU1451, and

ADAU1450. These tests were conducted at an ambient tempera-

ture of 105°C, with a completely full DSP program that executes

an endless loop of the most power intensive core calculations and

with all power supplies at their maximum values.

Thus, the conditions described in Table 19 are intended as a stress

test only and are not representative of realistic device operation

in a real-world application. In a system where the operating

conditions and limits outlined in the Specifications section of

this document are not exceeded, and where the device is mounted

to a printed circuit board (PCB) that follows the design

recommendations in the PCB Design Considerations section of

this document, the values that are listed represent the total power

consumption of the device. In actual applications, the power

consumption of the device is far lower. Table 20, Table 21, and

Table 22 show more realistic estimates for power consumption

in a typical use case.

Table 19. Worst Case Maximum Power Dissipation

Parameter Value Unit Test Conditions/Comments

AVDD,

DVDD, PVDD

During

ADAU1452

Operation

960 mW Ambient temperature = 105°C,

all supplies at maximum, full

DSP program using most power

intensive calculations; measure-

ment does not include IOVDD

AVDD,

DVDD, PVDD

During

ADAU1451

Operation

960 mW Ambient temperature = 105°C,

all supplies at maximum, full

DSP program using most power

intensive calculations; measure-

ment does not include IOVDD

AVDD,

DVDD, PVDD

During

ADAU1450

Operation

960 mW Ambient temperature = 105°C,

all supplies at maximum, full

DSP program using most power

intensive calculations; measure-

ment does not include IOVDD

Reset All

Supplies

570 mW Ambient temperature = 105°C,

all supplies at maximum, reset

mode enabled; measurement

does not include IOVDD

Table 20. ADAU1452 Typical Power Dissipation Estimates

Ambient

Temperature (°C)

Full Program (mW) Typical (mW)

25 420 250

85 700 420

105 885 530

Table 21. ADAU1451 Typical Power Dissipation Estimates

Ambient

Temperature (°C) Full Program (mW) Typical (mW)

25 420 250

85 700 420

105 885 530

Table 22. ADAU1450 Typical Power Dissipation Estimates

Ambient

Temperature (°C)

Full Program (mW) Typical (mW)

25 170 100

85 385 230

105 480 290

ESD CAUTION

Rev. C | Page 17 of 180

ADAU1452/ADAU1451/ADAU1450 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DGND

DVDD

SDATA_OUT3

BCLK_OUT3

LRCLK_OUT3/MP9

SDATA_OUT2

BCLK_OUT2

LRCLK_OUT2/MP8

MP7

MP6

SDATA_OUT1

BCLK_OUT1

LRCLK_OUT1/MP5

SDATA_OUT0

BCLK_OUT0

LRCLK_OUT0/MP4

IOVDD

DGND

ADAU1452/

ADAU1451/

ADAU1450

TOP VIEW

DVDD

SDATA_IN3

LRCLK_IN3/MP13

BCLK_IN3

SDATA_IN2

LRCLK_IN2/MP12

BCLK_IN2

THD_P

THD_M

SDATA_IN1

LRCLK_IN1/MP11

BCLK_IN1

SDATA_IN0

LRCLK_IN0/MP10

BCLK_IN0

IOVDD

DGND

IOVDD

VDRIVE

SPDIFIN

SPDIFOUT

AGND

AVDD

AUXADC0

AUXADC1

AUXADC2

AUXADC3

AUXADC4

AUXADC5

PGND

PVDD

PLLFILT

DGND

IOVDD

DVDD

XTALIN/MCLK

XTALOUT

CLKOUT

RESET

DGND

SS_M/MP0

MOSI_M/MP1

SCL_M/SCLK_M/MP2

SDA_M/MISO_M/MP3

MISO/SDA

SCLK/SCL

MOSI/ADDR1

SS/ADDR0

SELFBOOT

DVDD

DGND

11486-002

NOTES

1. THE EXPOSED PAD MUST BE GROUNDED BY SOLDERING IT TO A COPPER SQUARE

OF EQUIVALENT SIZE ON THE PCB. IDENTICAL COPPER SQUARES MUST EXIST ON

ALL LAYERS OF THE BOARD, CONNECTED BY VIAS, AND THEY MUST BE CONNECTED

TO A DEDICATED COPPER GROUND LAYER WITHIN THE PCB.

Figure 12. Pin Configuration

Table 23. Pin Function Descriptions

No. Mnemonic

Internal Pull

Resistor Description

1 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

2 IOVDD None Input/Output Supply, 1.8 V − 10% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to

Pin 1 (DGND).

3 VDRIVE None PNP Bipolar Junction Transistor-Base Drive Bias Pin for the Digital Supply Regulator. Connect

VDRIVE to the base of an external PNP pass transistor (STD2805 is recommended). If an

external supply is provided directly to DVDD, connect the VDRIVE pin to ground.

4 SPDIFIN None Input to the Integrated Sony/Philips Digital Interface Format Receiver. Disconnect this pin when

not in use. This pin is internally biased to IOVDD/2. This pin is nonfunctional on the ADAU1450

and should be left disconnected.

5 SPDIFOUT Configurable Output from the Integrated Sony/Philips Digital Interface Format Transmitter. Disconnect this

pin when not in use. This pin is internally biased to IOVDD/2. This pin is nonfunctional on the

ADAU1450 and should be left disconnected.

6 AGND None Analog Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common

ground plane.

7 AVDD None Analog (Auxiliary ADC) Supply. Must be 3.3 V ± 10%. Bypass this pin with decoupling capacitors

to Pin 6 (AGND).

8 AUXADC0 None Auxiliary ADC Input Channel 0. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

9 AUXADC1 None Auxiliary ADC Input Channel 1. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

Rev. C | Page 18 of 180

Data Sheet ADAU1452/ADAU1451/ADAU1450

No. Mnemonic

Internal Pull

Resistor Description

10 AUXADC2 None Auxiliary ADC Input Channel 2. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

11 AUXADC3 None Auxiliary ADC Input Channel 3. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

12 AUXADC4 None Auxiliary ADC Input Channel 4. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

13 AUXADC5 None Auxiliary ADC Input Channel 5. This pin reads an analog input signal and uses its value in the

DSP program. Disconnect this pin when not in use.

14 PGND None PLL Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common

ground plane.

15 PVDD None PLL Supply. Must be 3.3 V ± 10%. Bypass this pin with decoupling capacitors to Pin 14 (PGND).

16 PLLFILT None PLL Filter. The voltage on the PLLFILT pin, which is internally generated, is typically between

1.65 V and 2.10 V.

17 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

18 IOVDD None Input/Output Supply, 1.8 V − 10% to 3.3 V + 10%. Bypass this pin to Pin 17 (DGND) with

decoupling capacitors.

19 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

20 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal

regulator and external pass transistor. Bypass this pin to Pin 19 (DGND) with decoupling

capacitors.

21 XTALIN/MCLK None Crystal Oscillator Input (XTALIN)/Master Clock Input to the PLL (MCLK). This pin can be supplied

directly or generated by driving a crystal with the internal crystal oscillator via Pin 22 (XTALOUT).

If a crystal is used, refer to the circuit shown in Figure 15.

22 XTALOUT None Crystal Oscillator Output for Driving an External Crystal. If a crystal is used, refer to the circuit

shown in Figure 15. Disconnect this pin when not in use.

23 CLKOUT Configurable Master Clock Output. This pin drives a master clock signal to other ICs in the system. CLKOUT

can be configured to output a clock signal with a frequency of 1×, 2×, 4×, or 8× the frequency

of the divided clock signal being input to the PLL. Disconnect this pin when not in use.

RESET

Pull-down Active Low Reset Input. A reset is triggered on a high-to-low edge and exited on a low-to-high

edge. A reset event sets all RAMs and registers to their default values.

25 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

26 SS_M/MP0 Pull-up; nominally

250 kΩ; can be

disabled by a write

to control register

SPI Master/Slave Select Port (SS_M)/Multipurpose, General-Purpose Input/Output (MP0). When

in SPI master mode, this pin acts as the slave select signal to slave devices on the SPI bus. The

pin must go low at the beginning of a master SPI transaction and high at the end of a transaction.

This pin has an internal pull-up resistor that is nominally 250 kΩ. When the SELFBOOT pin is

held high and the

RESET

pin has a transition from low to high, Pin 26 sets the communications

protocol for self boot operation. If this pin is left floating, the SPI communications protocol is

used for self boot operation. If this pin has a 10 kΩ pull-down resistor to GND, the I

C communi-

cations protocol is used for self boot operation. When self boot operation is not used and this

pin is not needed as a general-purpose input or output, leave it disconnected.

27 MOSI_M/MP1 Pull-up; can be

disabled by a write

to control register

SPI Master Data Output Port (MOSI_M)/Multipurpose, General-Purpose Input/Output (MP1).

When in SPI master mode, this pin sends data from the SPI master port to slave devices on the

SPI bus. Disconnect this pin when not in use.

28 SCL_M/

SCLK_M/MP2

Pull-up; can be

disabled by a write

to control register

C Master Serial Clock Port (SCL_M)/SPI Master Mode Serial Clock (SCLK_M)/Multipurpose,

General-Purpose Input/Output (MP2). When in I

C master mode, this pin functions as an open

collector output and drives a serial clock to slave devices on the I

C bus; use a 2.0 kΩ pull-up

resistor to IOVDD on the line connected to this pin. When in SPI master mode, this pin drives

the clock signal to slave devices on the SPI bus. Disconnect this pin when not in use.

29 SDA_M/

MISO_M/MP3

Pull-up; can be

disabled by a write

to control register

C Master Port Serial Data (SDA_M)/SPI Master Mode Data Input (MISO_M)/Multipurpose,

General-Purpose Input/Output (MP3). When in I

C master mode, this pin functions as a bi-

directional open collector data line between the I

C master port and slave devices on the I

C bus;

use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When in SPI master mode,

this pin receives data from slave devices on the SPI bus. Disconnect this pin when not in use.

Rev. C | Page 19 of 180

ADAU1452/ADAU1451/ADAU1450 Data Sheet

No. Mnemonic

Internal Pull

Resistor Description

30 MISO/SDA Pull-up; can be

disabled by a write

to control register

SPI Slave Data Output Port (MISO)/I

C Slave Serial Data Port (SDA). In SPI slave mode, this pin

outputs data to the master device on the SPI bus. In I

C slave mode, this pin functions as a bi-

directional open collector data line between the I

C slave port and the master device on the

C bus; use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When this pin

is not in use, connect it to IOVDD with a 10.0 kΩ pull-up resistor.

31 SCLK/SCL Pull-up; can be

disabled by a write

to control register

SPI Slave Port Serial Clock (SCLK)/I

C Slave Port Serial Clock (SCL). In SPI slave mode, this pin

receives the serial clock signal from the master device on the SPI bus. In I

C slave mode, this pin

receives the serial clock signal from the master device on the I

C bus; use a 2.0 kΩ pull-up

resistor to IOVDD on the line connected to this pin. When this pin is not in use, connect it to

IOVDD with a 10.0 kΩ pull-up resistor.

32 MOSI/ADDR1 Pull-up; can be

disabled by a write

to control register

SPI Slave Port Data Input (MOSI)/I

C Slave Port Address MSB (ADDR1). In SPI slave mode, this pin

receives a data signal from the master device on the SPI bus. In I

C slave mode, this pin acts as

an input and sets the chip address of the I

C slave port, in conjunction with Pin 33 (SS/ADDR0).

33 SS/ADDR0 Pull-up, nominally

250 kΩ; can be

disabled by a write

to control register

SPI Slave Port Slave Select (SS)/I

C Slave Port Address LSB (ADDR0). In SPI slave mode, this pin

receives the slave select signal from the master device on the SPI bus. In I

C slave mode, this pin acts

as an input and sets the chip address of the I

C slave port in conjunction with Pin 32 (MOSI/ADDR1).

34 SELFBOOT Pull-up Self Boot Select. This pin allows the device to perform a self boot, in which it loads its RAM and

self boot operation the next time there is a rising edge on Pin 24 (

RESET

). When this pin is

connected to ground, no self boot operation is initiated. This pin can be connected to IOVDD

or to ground either directly or pulled up or down with a 1.0 kΩ or larger resistor.

35 DVDD None Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal

regulator and external pass transistor. Bypass this pin to Pin 36 (DGND) with decoupling

capacitors.

36 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

37 DGND None Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

38 IOVDD None Input/Output Supply, 1.8 V − 10% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to

Pin 37 (DGND).

39 LRCLK_OUT0/

MP4

Configurable Frame Clock, Serial Output Port 0 (LRCLK_OUT0)/Multipurpose, General-Purpose Input/Output

(MP4). This pin is bidirectional, with the direction depending on whether Serial Output Port 0 is

a master or slave. Disconnect this pin when not in use.

40 BCLK_OUT0 Configurable Bit Clock, Serial Output Port 0. This pin is bidirectional, with the direction depending on whether

the Serial Output Port 0 is a master or slave. Disconnect this pin when not in use.

SDATA_OUT0

Configurable

Serial Data Output Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8-channel,

and 16-channel modes. Disconnect this pin when not in use.

42 LRCLK_OUT1/

MP5

Configurable Frame Clock, Serial Output Port 1 (LRCLK_OUT1)/Multipurpose, General-Purpose Input/Output

(MP5). This pin is bidirectional, with the direction depending on whether Serial Output Port 1 is

a master or slave. Disconnect this pin when not in use.

43 BCLK_OUT1 Configurable Bit Clock, Serial Output Port 1. This pin is bidirectional, with the direction depending on whether

Output Serial Port 1 is a master or slave. Disconnect this pin when not in use.

44 SDATA_OUT1 Configurable Serial Data Output Port 1 (Channel 16 to Channel 31). Capable of 2-channel, 4-channel, 8-channel,

and 16-channel modes. Disconnect this pin when not in use.

45 MP6 Configurable Multipurpose, General-Purpose Input/Output 6. Disconnect this pin when not in use.

46 MP7 Configurable Multipurpose, General-Purpose Input/Output 7. Disconnect this pin when not in use.

47 LRCLK_OUT2/

MP8

Configurable Frame Clock, Serial Output Port 2 (LRCLK_OUT2)/Multipurpose, General-Purpose Input/Output

(MP8). This pin is bidirectional, with the direction depending on whether Serial Output Port 2 is

a master or slave. Disconnect this pin when not in use.

48 BCLK_OUT2 Configurable Bit Clock, Serial Output Port 2. This pin is bidirectional, with the direction depending on whether

Serial Output Port 2 is a master or slave. Disconnect this pin when not in use.

49 SDATA_OUT2 Configurable Serial Data Output Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel, 8-channel,

or flexible TDM mode. Disconnect this pin when not in use.

50 LRCLK_OUT3/

MP9

Configurable Frame Clock, Serial Output Port 3 (LRCLK_OUT3)/Multipurpose, General-Purpose Input/Output

(MP9). This pin is bidirectional, with the direction depending on whether Serial Output Port 3 is

a master or slave. Disconnect this pin when not in use.

Rev. C | Page 20 of 180

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