超低功耗EFM32G微控制器：Cortex-M3性能与节能革命

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EFM32G系列是Silicon Labs公司推出的一款革命性的8到32位微控制器，其核心是一款高效的32位ARM Cortex-M3处理器，最高运行速度可达32MHz。这款微控制器在节能性能上独树一帜，特别适合对功耗敏感的应用，如物联网（IoT）、无线传感器网络（WSN）以及电池供电设备。该系列的特点包括： 1. **卓越的能效表现**：在运行模式下，最低功耗仅为180 µA/MHz，这意味着在执行任务时，它能够提供出色的性能同时保持极低的电能消耗。当仅启用Real-Time Counter、Brown-out保护和满RAM及寄存器保留功能时，待机模式下的电流甚至低至900 nA，这对于延长设备电池寿命至关重要。 2. **内存容量**：EFM32F128型号提供了高达128 kB的闪存存储和16 kB的随机访问存储器（RAM），满足了不同规模项目的需求，尤其是对于那些对存储空间有较高要求的应用。 3. **自主与节能外设**：该系列集成了一系列自主且能源效率高的外设，例如计时器、通信接口等，使得开发者能够在不影响整体性能的前提下，优化设备的功耗管理。 4. **高度集成**：芯片内集成了高性能模拟电路，这减少了外部组件的需求，简化了设计，降低了成本，并提高了系统的整体效能。 5. **标准Cortex-M3性能**：作为工业标准的32位处理器，Cortex-M3提供了强大的计算能力和丰富的指令集，支持高效处理复杂的控制任务。 6. **广泛应用领域**：EFM32G微控制器适用于多种典型应用，如工业自动化、智能家居、健康监测、智能电网设备以及能源管理系统，因为其能在各种条件下提供可靠的低功耗解决方案。 7. **版本更新**：该手册发布于2017年2月，Gecko Family Rev1.31，表明EFM32G系列持续进行优化和改进，以适应不断变化的技术需求。 EFM32G系列微控制器凭借其出色的能效、丰富的功能和广泛的适用性，成为追求高效、低功耗设计者的首选工具。无论是开发高精度的工业设备，还是设计需要长时间运行的可穿戴设备，EFM32G都能提供理想的平台。

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Figure 5.2. System Address Space

The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32G. When

running code located in SRAM starting at this address, the Cortex-M3 uses the System bus to fetch

instructions. This results in reduced performance as the Cortex-M3 accesses stack, other data in SRAM

and peripherals using the System bus. To be able to run code from SRAM efficiently, the SRAM is also

mapped in the code space at address 0x10000000. When running code from this space, the Cortex-M3

fetches instructions through the I/D-Code bus interface, leaving the System bus for data access. The

SRAM mapped into the code space can however only be accessed by the CPU, i.e. not the DMA.

5.2.1 Bit-banding

The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and

0x42000000 respectively. Read and write operations to these regions are converted into masked single-

bit reads and atomic single-bit writes to the embedded SRAM and peripherals of the EFM32G.

The standard approach to modify a single register or SRAM bit in the aliased regions, requires software

to read the value of the byte, half-word or word containing the bit, modify the bit, and then write the byte,

half-word or word back to the register or SRAM address. Using bit-banding, this read-modify-write can

be done in a single atomic operation. As read-writeback, bit-masking and bit-shift operations are not

necessary in software, code size is reduced and execution speed improved.

The bit-band regions allows addressing each individual bit in the SRAM and peripheral areas of the

memory map. To set or clear a bit in the embedded SRAM, write a 1 or a 0 to the following address:

Memory SRAM Area Set/Clear Bit

bit_address = 0x22000000 + (address – 0x20000000) × 32 + bit × 4, (5.1)

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Memory Wait Cycles with Clock Equal or Faster than HFCORECLK

cycles

= 2 + N

slave cycles

, (5.3)

where N

slave cycles

is the wait cycles introduced by the slave.

When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are

introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per

access, in addition to master arbitration, is given by:

Memory Wait Cycles with Clock Slower than CPU

cycles

= (2 + N

slave cycles

) x f

HFCORECLK

HFPERCLK

, (5.4)

where N

slave cycles

is the number of wait cycles introduced by the slave.

For general register access, N

slave cycles

= 1.

More details on clocks and prescaling can be found in Chapter 11 (p. 94) .

5.3 Access to Low Energy Peripherals (Asynchronous Registers)

5.3.1 Introduction

The Low Energy Peripherals are capable of running when the high frequency oscillator and core system

is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to

perform tasks while the system energy consumption is minimal.

The Low Energy Peripherals are:

• Liquid Crystal Display driver - LCD

• Low Energy Timer - LETIMER

• Low Energy UART - LEUART

• Pulse Counter - PCNT

• Real Time Counter - RTC

• Watchdog - WDOG

All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low

Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints

on how register accesses can be done, as described in the following sections.

5.3.1.1 Writing

Every Low Energy Peripheral has one or more registers with data that needs to be synchronized

into the Low Energy clock domain to maintain data consistency and predictable operation. Due to

synchronization, the write operation requires 3 positive edges of the clock of the Low Energy Peripheral

being accessed. Such registers are marked "Asynchronous" in their description header.

See Figure 5.3 (p. 20) for a more detailed overview of the writing operation.

After writing data to a register which value is to be synchronized into the Low Energy clock domain, a

corresponding busy flag in the <module_name>_SYNCBUSY register (e.g. RTC_SYNCBUSY) is set.

This flag is set as long as synchronization is in progress and is cleared upon completion.

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