NAU8401: 低功耗高质音频系统datasheet v2.4

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NAU8401是一款专为便携式应用设计的高性能24位立体声音频DAC（数字模拟转换器）数据手册，其最新版本Rev2.4发布于2013年10月。这款设备集成了精密的音频处理能力，旨在简化音频系统的集成，提供全面的音频输出解决方案。 NAU8401的核心功能包括两个24位立体声DAC，能够确保高保真度的音频质量。它内置了多个音频输出接口，如扬声器驱动器、耳机和立体声线路输出，方便用户根据需要选择合适的音频输出路径。该设备特别强调信号处理性能，内置了5频段均衡器，能够改善音质的均衡性；此外，还配备了3-D音频增强器，通过数字技术提升空间音频体验；以及数字限制器/动态范围压缩器，确保音频播放过程中的动态范围控制和稳定性。 NAU8401的数字接口设计非常灵活，既可以作为主设备，也可以作为从属设备，这在构建多媒体系统时提供了更大的灵活性。它内部集成了一款精密的内置分频NPLL（噪声相位锁定环路），可以准确地根据系统时钟（8MHz到33MHz）生成音频采样率时钟，确保音频同步。在供电方面，NAU8401兼容宽电压范围，可以从2.5V到3.6V的模拟电源工作，而数字核心部分甚至可以低至1.7V，以最大程度地节省功耗。同时，为了支持外部设备，扬声器BTL输出对和两个辅助线路输出可接受5V电压，这增加了与不同外部设备的兼容性。 NAU8401凭借其强大的音频处理能力、广泛的接口选项以及出色的节能特性，为现代便携式设备的音频设计提供了高效且灵活的解决方案，是音频开发人员构建高质量音频系统的重要工具。

NAU8401

Datasheet Rev 2.4 Page 12 of 69 March, 2014

2 Power Supply

This device has been designed to operate reliably using a wide range of power supply conditions and power-

on/power-off sequences. There are no special requirements for the sequence or rate at which the various power

supply pins change. Any supply can rise or fall at any time without harm to the device. However, pops and clicks

may result from some sequences. Optimum handling of hardware and software power-on and power-off sequencing

is described in more detail in the Applications section of this document.

2.1.1 Power-On Reset

The NAU8401 does not have an external reset pin. The device reset function is automatically generated internally

when power supplies are too low for reliable operation. The internal reset is generated any time that either VDDA

or VDDC is lower than is required for reliable maintenance of internal logic conditions. The reset threshold voltage

for VDDA and VDDC is approximately 0.5Vdc. If both VDDA and VDDC are being reduced at the same time, the

threshold voltage may be slightly lower. Note that these are much lower voltages than are required for normal

operation of the chip. These values are mentioned here as general guidance as to overall system design.

If either VDDA or VDDC is below its respective threshold voltage, an internal reset condition is asserted. During

this time, all registers and controls are set to the hardware determined initial conditions. Software access during this

time will be ignored, and any expected actions from software activity will be invalid.

When both VDDA and VDDC reach a value above their respective thresholds, an internal reset pulse is generated

which extends the reset condition for an additional time. The duration of this extended reset time is approximately

50 microseconds, but not longer than 100 microseconds. The reset condition remains asserted during this time. If

either VDDA or VDDC at any time becomes lower than its respective threshold voltage, a new reset condition will

result. The reset condition will continue until both VDDA and VDDC again higher than their respective

thresholds. After VDDA and VDDC are again both greater than their respective threshold voltage, a new reset pulse

will be generated, which again will extend the reset condition for not longer than an additional 100 microseconds.

2.1.2 Power Related Software Considerations

There is no direct way for software to determine that the device is actively held in a reset condition. If there is a

possibility that software could be accessing the device sooner than 100 microseconds after the VDDA and VDDC

supplies are valid, the reset condition can be determined indirectly. This is accomplished by writing a value to any

choice of register for this purpose may be dependent on the system design, and it is recommended the system

engineer choose the register and register test bit for this purpose. After writing the value, software will then read

back the same register. When the register test bit reads back as the new value, instead of the power-on reset initial

value, software can reliably determine that the reset condition has ended.

Although it is not required, it is strongly recommended that a Software Reset command should be issued after

power-on and after the power-on reset condition is ended. This will help insure reliable operation under every

power sequencing condition that could occur.

If there is any possibility that VDDA or VDDC could be unreliable during system operation, software may be

designed to monitor whether a power-on reset condition has happened. This can be accomplished by writing a test

bit to a register that is different from the power-on initial conditions. This test bit should be a bit that is never used

for any other reason, and does not affect desired operation in any way. Then, software at any time can read this bit

to determine if a power-on reset condition has occurred. If this bit ever reads back other than the test value, then

software can reliably know that a power-on reset event has occurred. Software can subsequently re-initialize the

device and the system as required by the system design.

2.1.3 Software Reset

All chip registers can be reset to power-on default conditions by writing any value to register 0, using any of the

control modes. Writing valid data to any other register disables the reset, but all registers need to have the correct

operating data written. See the applications section on powering NAU8401 up for information on avoiding pops and

clicks after a software reset.

NAU8401

Datasheet Rev 2.4 Page 13 of 69 March, 2014

3 Input Path Detailed Description

The NAU8401 provides two analog inputs that are buffered, scaled, optionally muted, and then made available to

the output mixers. The output mixers enable a wide range of possible routing of these inputs to the analog output

pins, as well as mixing with the output signal from the DAC subsystem.

These inputs are maintained at a DC bias at approximately ½ of the AVDD supply voltage. Connections to these

inputs should be AC-coupled by means of DC blocking capacitors suitable for the device application. If not used,

these input pins should not be left not-connected and muted in the software register controls.

The RINPUT signal may additionally be routed to the Right Speaker Submixer in the analog output section. This

path enables a sound to be output from the LSPKOUT speaker output, but without being audible anywhere else in

the system. One purpose of this path is to support a traditional “beep” sound, such as from a microprocessor toggle

bit. This is a historical application scenario which is now uncommon.

These inputs are affected by the following registers:

LMAIN MIXER or RMAIN MIXER if used (see output mixer section)

RSPK SUBMIXER if used (see Right Speaker Submixer section)

3.1 Analog Input Impedance and Variable Gain Stage Topology

Each analog input pin is supported by the circuit shown here as a simplified schematic. The gain value changes

affect input impedance as detailed in this section. If a path is in the “not selected” condition, then the input

impedance will be in a high impedance condition and the input signal will be muted. If an external input pin is not

used anywhere in the system, it will be coupled to a DC tie-off of approximately 30kΩ coupled to VREF. The

unused input tie-off function is explained in more detail in the Application Information section of this document.

Input

-15 dB to

+6.0 dB

To Next

Stage

Gain Value

Adjustment

“Not Selected”

Switch

VREF

Figure 2: Variable Gain Stage Simplified Schematic

The input impedance presented to these inputs depends on the input routing choices and gain values. The nominal

resistive input impedances presented to signal pins that are directly routed to an output mixer are listed in the

following table. The RINPUT signal may also be connected to the Right Speaker Submixer. If both RINPUT signal

paths are connected, then the RINPUT input impedance will be the parallel combination of the two paths.

Inputs

Gain

(dB)

Impedance

(kΩ)

LINPUT & RINPUT to

bypass amp

RINPUT to

RSPK SUBMIXER amp

-15

225

-12

159

-9

113

-6

-3

Table 1: Analog Input and RSPK SUBMIXER Input Impedances

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