Intel ICH9 官方技术手册：开发x86主板驱动的重要参考资料

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"Intel I/O Controller Hub9 (ICH9) 参考及数据手册，对于开发x86主板驱动程序非常有帮助。" Intel I/O Controller Hub9 (ICH9) 是英特尔公司推出的一款南桥芯片，主要用于配合x86架构的处理器，提供多种I/O接口和扩展功能。该芯片家族包括82801IB (ICH9), 82801IR (ICH9R), 82801IH (ICH9DH), 82801IO (ICH9DO), 82801IBM (ICH9M), 82801IEM (ICH9M-E)，以及ICH9M-SFF等不同型号，各自针对不同的市场和应用需求。 datasheet 提供了详细的技术规格和设计指南，对于开发者来说是必不可少的参考资料。文档编号为316972-004，发布日期为2008年8月，包含了对这些ICH9系列芯片的详细描述，如功能特性、电气特性、接口规范、系统配置选项等。在硬件设计和驱动开发中，理解ICH9的功能是至关重要的。以下是一些关键知识点： 1. **PCI Express（PCIe）支持**：ICH9支持PCI Express接口，提供了多个PCIe通道，用于连接显卡、网卡等高速外设，提高了数据传输速率。 2. **SATA（Serial ATA）控制器**：ICH9集成了SATA控制器，支持SATA 3Gbps接口，为存储设备提供高速连接。 3. **USB（Universal Serial Bus）控制器**：提供多个USB 2.0接口，方便连接各种USB设备。 4. **集成RAID功能**：部分型号的ICH9支持RAID (Redundant Array of Independent Disks) 功能，可以实现数据冗余和性能提升。 5. **内存控制器**：虽然ICH9不直接控制内存，但它与北桥芯片（通常与CPU封装在一起）交互，支持DDR2内存，并处理内存的时序和控制信号。 6. **GPIO（General Purpose Input/Output）**：ICH9包含GPIO端口，允许系统进行灵活的输入输出控制。 7. **中断管理**：ICH9处理来自各个设备的中断请求，通过中断重映射技术提高系统响应速度。 8. **电源管理**：支持ACPI（Advanced Configuration and Power Interface）标准，实现节能和唤醒功能。 9. **热插拔和唤醒功能**：ICH9支持USB设备的热插拔，以及网络唤醒（Wake-on-LAN）等功能。 10. **安全特性**：ICH9还包括对硬件级安全的支持，如TPM（Trusted Platform Module）接口，用于加密和安全认证。在开发驱动程序时，开发者需要深入理解这些特性，并按照datasheet提供的指导进行编程，确保驱动与硬件的正确交互，同时遵循Intel的销售条款和条件。值得注意的是，Intel明确指出其产品不适用于医疗、生命维持或生命保护应用，因此在这些领域需要额外的验证和考虑。总体来说，ICH9参考和数据手册为开发人员提供了全面的硬件信息，是构建基于Intel平台系统的软件和硬件工程师不可或缺的工具。通过深入学习和理解这些内容，可以有效地优化系统性能和稳定性。

16 Intel

I/O Controller Hub 9 (ICH9) Family Datasheet

13.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0)................................474

13.5.1 APIC Register Map (LPC I/F—D31:F0)......................................................474

13.5.2 IND—Index Register (LPC I/F—D31:F0)...................................................474

13.5.3 DAT—Data Register (LPC I/F—D31:F0)....................................................475

13.5.4 EOIR—EOI Register (LPC I/F—D31:F0) ....................................................475

13.5.5 ID—Identification Register (LPC I/F—D31:F0)...........................................476

13.5.6 VER—Version Register (LPC I/F—D31:F0) ................................................476

13.5.7 REDIR_TBL—Redirection Table (LPC I/F—D31:F0).....................................477

13.6 Real Time Clock Registers.................................................................................479

13.6.1 I/O Register Address Map ......................................................................479

13.6.2 Indexed Registers.................................................................................480

13.6.2.1 RTC_REGA—Register A ............................................................481

13.6.2.2 RTC_REGB—Register B (General Configuration)...........................482

13.6.2.3 RTC_REGC—Register C (Flag Register).......................................483

13.6.2.4 RTC_REGD—Register D (Flag Register).......................................483

13.7 Processor Interface Registers (LPC I/F—D31:F0)..................................................484

13.7.1 NMI_SC—NMI Status and Control Register

(LPC I/F—D31:F0) ................................................................................484

13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)

13.7.3 PORT92—Fast A20 and Init Register (LPC I/F—D31:F0) .............................485

13.7.4 COPROC_ERR—Coprocessor Error Register

(LPC I/F—D31:F0) ................................................................................486

13.7.5 RST_CNT—Reset Control Register (LPC I/F—D31:F0).................................486

13.8 Power Management Registers (PM—D31:F0) .......................................................487

13.8.1 Power Management PCI Configuration Registers

(PM—D31:F0) ......................................................................................487

13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register

(PM—D31:F0).........................................................................488

13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register

(PM—D31:F0).........................................................................490

13.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register

(PM—D31:F0).........................................................................492

13.8.1.4 GEN_PMCON_LOCK- General Power Management

Configuration Lock Register ......................................................494

13.8.1.5 C5_EXIT_TIMING_CNT- C5 Exit Timing Register (Mobile Only).......495

13.8.1.6 Cx-STATE_CNF—Cx State Configuration Register

(PM—D31:F0) (Mobile Only, Except Bit 2)...................................496

13.8.1.7 C4-TIMING_CNT—C4 Timing Control Register

(PM—D31:F0) (Mobile Only) .....................................................497

13.8.1.8 BM_BREAK_EN Register (PM—D31:F0) (Mobile Only) ...................498

13.8.1.9 PMIR—Power Management Initialization Register (PM—D31:F0).....499

13.8.1.10GPIO_ROUT—GPIO Routing Control Register

(PM—D31:F0).........................................................................499

13.8.2 APM I/O Decode ...................................................................................500

13.8.2.1 APM_CNT—Advanced Power Management Control Port Register.....500

13.8.2.2 APM_STS—Advanced Power Management Status Port Register ......500

13.8.3 Power Management I/O Registers ...........................................................501

13.8.3.1 PM1_STS—Power Management 1 Status Register.........................503

13.8.3.2 PM1_EN—Power Management 1 Enable Register..........................506

13.8.3.3 PM1_CNT—Power Management 1 Control....................................507

13.8.3.4 PM1_TMR—Power Management 1 Timer Register.........................508

13.8.3.5 PROC_CNT—Processor Control Register......................................508

13.8.3.6 LV2 — Level 2 Register ............................................................510

13.8.3.7 LV3—Level 3 Register (Mobile Only)...........................................510

13.8.3.8 LV4—Level 4 Register (Mobile Only)...........................................510

13.8.3.9 LV5—Level 5 Register (Mobile Only)...........................................511

13.8.3.10LV6—Level 6 Register (Mobile Only)...........................................511

Intel

I/O Controller Hub 9 (ICH9) Family Datasheet 17

13.8.3.11GPE0_STS—General Purpose Event 0 Status Register .................. 512

13.8.3.12GPE0_EN—General Purpose Event 0 Enables Register .................. 515

13.8.3.13SMI_EN—SMI Control and Enable Register ................................. 517

13.8.3.14SMI_STS—SMI Status Register................................................. 519

13.8.3.15ALT_GP_SMI_EN—Alternate GPI SMI Enable Register .................. 521

13.8.3.16ALT_GP_SMI_STS—Alternate GPI SMI Status Register ................. 522

13.8.3.17UPRWC—USB Per-Port Registers Write Control............................ 522

13.8.3.18GPE_CNTL— General Purpose Control Register............................ 523

13.8.3.19DEVACT_STS — Device Activity Status Register .......................... 523

13.8.3.20PM2_CNT—Power Management 2 Control (Mobile Only)................ 524

13.8.3.21C3_RES— C3 Residency Register (Mobile Only)........................... 524

13.8.3.22C5_RES— C5 Residency Register (Mobile Only)........................... 525

13.9 System Management TCO Registers (D31:F0)..................................................... 526

13.9.1 TCO_RLD—TCO Timer Reload and Current Value Register .......................... 526

13.9.2 TCO_DAT_IN—TCO Data In Register....................................................... 527

13.9.3 TCO_DAT_OUT—TCO Data Out Register .................................................. 527

13.9.4 TCO1_STS—TCO1 Status Register .......................................................... 527

13.9.5 TCO2_STS—TCO2 Status Register .......................................................... 529

13.9.6 TCO1_CNT—TCO1 Control Register......................................................... 531

13.9.7 TCO2_CNT—TCO2 Control Register......................................................... 532

13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers....................................... 532

13.9.9 TCO_WDCNT—TCO Watchdog Control Register......................................... 533

13.9.10SW_IRQ_GEN—Software IRQ Generation Register .................................... 533

13.9.11TCO_TMR—TCO Timer Initial Value Register............................................. 533

13.10 General Purpose I/O Registers (D31:F0)............................................................. 534

13.10.1GPIO_USE_SEL—GPIO Use Select Register [31:0] .................................... 535

13.10.2GP_IO_SEL—GPIO Input/Output Select Register [31:0]............................. 535

13.10.3GP_LVL—GPIO Level for Input or Output Register [31:0]........................... 536

13.10.4GPO_BLINK—GPO Blink Enable Register [31:0] ........................................ 536

13.10.5GP_SER_BLINK[31:0]—GP Serial Blink [31:0].......................................... 537

13.10.6GP_SB_CMDSTS[31:0]—GP Serial Blink Command Status [31:0]................ 538

13.10.7GP_SB_DATA[31:0]—GP Serial Blink Data [31:0] ..................................... 538

13.10.8GPI_INV—GPIO Signal Invert Register [31:0]........................................... 539

13.10.9GPIO_USE_SEL2—GPIO Use Select 2 Register [60:32] .............................. 539

13.10.10GP_IO_SEL2—GPIO Input/Output Select 2 Register [60:32] ..................... 540

13.10.11GP_LVL2—GPIO Level for Input or Output 2 Register [63:32] ................... 540

14 SATA Controller Registers (D31:F2)....................................................................... 541

14.1 PCI Configuration Registers (SATA–D31:F2)........................................................ 541

14.1.1 VID—Vendor Identification Register (SATA—D31:F2) ................................ 542

14.1.2 DID—Device Identification Register (SATA—D31:F2)................................. 543

14.1.3 PCICMD—PCI Command Register (SATA–D31:F2)..................................... 543

14.1.4 PCISTS — PCI Status Register (SATA–D31:F2)......................................... 544

14.1.5 RID—Revision Identification Register (SATA—D31:F2)............................... 545

14.1.6 PI—Programming Interface Register (SATA–D31:F2)................................. 545

14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h .......... 545

14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .......... 546

14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h .......... 546

14.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ........................................ 546

14.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2).................... 547

14.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2)................... 547

14.1.10HTYPE—Header Type (SATA–D31:F2) ..................................................... 547

14.1.11PCMD_BAR—Primary Command Block Base Address

14.1.12PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F2).................................................................................... 548

18 Intel

I/O Controller Hub 9 (ICH9) Family Datasheet

14.1.13SCMD_BAR—Secondary Command Block Base Address

14.1.14SCNL_BAR—Secondary Control Block Base Address

14.1.15BAR — Legacy Bus Master Base Address Register

(SATA–D31:F2)....................................................................................549

14.1.16ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA Index

Data Pair Base Address (SATA–D31:F2)...................................................549

14.1.16.1When SCC is not 01h...............................................................549

14.1.16.2When SCC is 01h ....................................................................550

14.1.17SVID—Subsystem Vendor Identification Register (SATA–D31:F2)................550

14.1.18SID—Subsystem Identification Register (SATA–D31:F2).............................550

14.1.19CAP—Capabilities Pointer Register (SATA–D31:F2)....................................550

14.1.20INT_LN—Interrupt Line Register (SATA–D31:F2).......................................551

14.1.21INT_PN—Interrupt Pin Register (SATA–D31:F2)........................................551

14.1.22IDE_TIM — IDE Timing Register (SATA–D31:F2).......................................551

14.1.23PID—PCI Power Management Capability Identification

14.1.24PC—PCI Power Management Capabilities Register

(SATA–D31:F2)....................................................................................552

14.1.25PMCS—PCI Power Management Control and Status

14.1.26MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2) 553

14.1.27MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2).........554

14.1.28MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2).......555

14.1.29MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) ............555

14.1.30MAP—Address Map Register (SATA–D31:F2).............................................556

14.1.31PCS—Port Control and Status Register (SATA–D31:F2)..............................556

14.1.32SCLKCG - SATA Clock Gating Control Register ..........................................559

14.1.33SCLKGC - SATA Clock General Configuration Register ................................560

14.1.33.1SATACR0—SATA Capability Register 0 (SATA–D31:F2).................561

14.1.33.2SATACR1—SATA Capability Register 1 (SATA–D31:F2).................561

14.1.34FLRCID—FLR Capability ID (SATA–D31:F2) ..............................................562

14.1.35FLRCLV—FLR Capability Length and Version (SATA–D31:F2).......................562

14.1.36FLRC—FLR Control (SATA–D31:F2) .........................................................563

14.1.37ATC—APM Trapping Control Register (SATA–D31:F2).................................563

14.1.38ATS—APM Trapping Status Register (SATA–D31:F2)..................................564

14.1.39SP Scratch Pad Register (SATA–D31:F2)..................................................564

14.1.40BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ...........................565

14.1.41BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ........................567

14.1.42BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ........................567

14.2 Bus Master IDE I/O Registers (D31:F2)...............................................................568

14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) ..........................569

14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)................................570

14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

14.2.4 AIR—AHCI Index Register (D31:F2) ........................................................571

14.2.5 AIDR—AHCI Index Data Register (D31:F2)...............................................571

14.3 Serial ATA Index/Data Pair Superset Registers.....................................................572

14.3.1 SINDX – Serial ATA Index (D31:F2) ........................................................572

14.3.2 SDATA – Serial ATA Data (D31:F2) .........................................................573

14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2).............................574

14.3.2.2 PxSCTL — Serial ATA Control Register (D31:F2) ..........................575

14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2)...............................576

14.4 AHCI Registers (D31:F2) ..................................................................................577

14.4.1 AHCI Generic Host Control Registers (D31:F2)..........................................578

Intel

I/O Controller Hub 9 (ICH9) Family Datasheet 19

14.4.1.1 CAP—Host Capabilities Register (D31:F2)................................... 578

14.4.1.2 GHC—Global ICH9 Control Register (D31:F2).............................. 580

14.4.1.3 IS—Interrupt Status Register (D31:F2)...................................... 581

14.4.1.4 PI—Ports Implemented Register (D31:F2).................................. 582

14.4.1.5 VS—AHCI Version (D31:F2) ..................................................... 583

14.4.1.6 CCC_CTL—Command Completion Coalescing Control

14.4.1.7 CCC_Ports—Command Completion Coalescing Ports

14.4.1.8 EM_LOC—Enclosure Management Location Register (D31:F2) ....... 584

14.4.1.9 EM_CTRL—Enclosure Management Control Register (D31:F2) ....... 585

14.4.2 Vendor Specific Registers (D31:F2)......................................................... 586

14.4.2.1 VSP—Vendor Specific (D31:F2)................................................. 586

14.4.3 Port Registers (D31:F2) ........................................................................ 586

14.4.3.1 PxCLB—Port [5:0] Command List Base Address Register

(D31:F2) ............................................................................... 589

14.4.3.2 PxCLBU—Port [5:0] Command List Base Address Upper

32-Bits Register (D31:F2)........................................................ 589

14.4.3.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2).................. 590

14.4.3.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits

14.4.3.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2).................... 591

14.4.3.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2).................... 592

14.4.3.7 PxCMD—Port [5:0] Command Register (D31:F2)......................... 594

14.4.3.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) .................... 597

14.4.3.9 PxSIG—Port [5:0] Signature Register (D31:F2)........................... 598

14.4.3.10PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2).............. 599

14.4.3.11PxSCTL — Port [5:0] Serial ATA Control Register (D31:F2)........... 600

14.4.3.12PxSERR—Port [5:0] Serial ATA Error Register (D31:F2)................ 601

14.4.3.13PxSACT—Port [5:0] Serial ATA Active (D31:F2) .......................... 603

14.4.3.14PxCI—Port [5:0] Command Issue Register (D31:F2).................... 603

15 SATA Controller Registers (D31:F5)....................................................................... 605

15.1 PCI Configuration Registers (SATA–D31:F5)........................................................ 605

15.1.1 VID—Vendor Identification Register (SATA—D31:F5) ................................ 606

15.1.2 DID—Device Identification Register (SATA—D31:F5)................................. 607

15.1.3 PCICMD—PCI Command Register (SATA–D31:F5)..................................... 607

15.1.4 PCISTS — PCI Status Register (SATA–D31:F5)......................................... 608

15.1.5 RID—Revision Identification Register (SATA—D31:F5)............................... 608

15.1.6 PI—Programming Interface Register (SATA–D31:F5)................................. 609

15.1.7 SCC—Sub Class Code Register (SATA–D31:F5) ........................................ 609

15.1.8 BCC—Base Class Code Register (SATA–D31:F5) ....................................... 609

15.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F5)................... 610

15.1.10PCMD_BAR—Primary Command Block Base Address

15.1.11PCNL_BAR—Primary Control Block Base Address Register

(SATA–D31:F5).................................................................................... 610

15.1.12SCMD_BAR—Secondary Command Block Base Address

15.1.13SCNL_BAR—Secondary Control Block Base Address

15.1.14BAR — Legacy Bus Master Base Address Register

(SATA–D31:F5).................................................................................... 612

15.1.15SIDPBA — SATA Index/Data Pair Base Address Register

(SATA–D31:F5).................................................................................... 612

15.1.16SVID—Subsystem Vendor Identification Register

(SATA–D31:F5).................................................................................... 613

15.1.17SID—Subsystem Identification Register (SATA–D31:F5)............................ 613

20 Intel

I/O Controller Hub 9 (ICH9) Family Datasheet

15.1.18CAP—Capabilities Pointer Register (SATA–D31:F5)....................................613

15.1.19INT_LN—Interrupt Line Register (SATA–D31:F5).......................................613

15.1.20INT_PN—Interrupt Pin Register (SATA–D31:F5)........................................613

15.1.21IDE_TIM — IDE Timing Register (SATA–D31:F5).......................................614

15.1.22PID—PCI Power Management Capability Identification

15.1.23PC—PCI Power Management Capabilities Register

(SATA–D31:F5)....................................................................................614

15.1.24PMCS—PCI Power Management Control and Status

15.1.25MID—Message Signal Interrupt Identifier (SATA–D31:F5) ..........................615

15.1.26MC—Message Signal Interrupt Message Control (SATA–D31:F5)..................616

15.1.27MA—Message Signal Interrupt Message Address (SATA–D31:F5).................616

15.1.28MD—Message Signal Interrupt Message Data (SATA–D31:F5).....................616

15.1.29MAP—Address Map Register (SATA–D31:F5)16.........................................617

15.1.30PCS—Port Control and Status Register (SATA–D31:F5)..............................618

15.1.31SATACR0— SATA Capability Register 0 (SATA–D31:F5) .............................619

15.1.32SATACR1— SATA Capability Register 1 (SATA–D31:F5) .............................619

15.1.33FLRCID— FLR Capability ID (SATA–D31:F5) .............................................619

15.1.34FLRCLV— FLR Capability Length and Value (SATA–D31:F5) ........................620

15.1.35FLRCTRL— FLR Control (SATA–D31:F5) ...................................................620

15.1.36ATC—APM Trapping Control Register (SATA–D31:F5).................................621

15.1.37ATC—APM Trapping Control (SATA–D31:F5).............................................621

15.2 Bus Master IDE I/O Registers (D31:F5)...............................................................622

15.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) ..........................623

15.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)................................624

15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer

15.3 AHCI Index Data Pair Registers..........................................................................625

15.3.1 INDEX—AHCI Index Register (D31:F5) ....................................................625

15.3.2 Data—AHCI Data Register (D31:F5)........................................................625

15.4 Serial ATA Index/Data Pair Superset Registers.....................................................626

15.4.1 SINDX—SATA Index Register (D31:F5)....................................................626

15.4.2 SDATA—SATA Index Data Register (D31:F5)............................................626

15.4.2.1 PxSSTS—Serial ATA Status Register (D31:F5).............................627

15.4.2.2 PxSCTL — Serial ATA Control Register (D31:F5) ..........................628

15.4.2.3 PxSERR—Serial ATA Error Register (D31:F5)...............................629

16 UHCI Controllers Registers ....................................................................................631

16.1 PCI Configuration Registers

(USB—D29:F0/F1/F2/F3, D26:F0/F1/F2).............................................................631

16.1.1 VID—Vendor Identification Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)..................................................632

16.1.2 DID—Device Identification Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)..................................................632

16.1.3 PCICMD—PCI Command Register (USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)...633

16.1.4 PCISTS—PCI Status Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)..................................................634

16.1.5 RID—Revision Identification Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)..................................................634

16.1.6 PI—Programming Interface Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)..................................................635

16.1.7 SCC—Sub Class Code Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)..................................................635

16.1.8 BCC—Base Class Code Register

(USB—D29:F0/F1/F2/F3, D26:F0/F1/F2)..................................................635

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Intel ICH9 官方技术手册：开发x86主板驱动的重要参考资料

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