Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces, Rev. 2
4 Freescale Semiconductor
Designer’s Checklist
24. Suggest routing order within the DDR2 interface:
1) Data, 2) Address/Command, 3) Control, 4) Clocks, and 5) Power
This order allows the clocks to be tuned easily to the other signal groups. It also assumes an open
critical layer on which clocks are freely routed.
25. Global items—
• Do not route any DDR2 signals overs splits or voids.
• Traces routed near the edge of a reference plane should maintain at least 30–40 mil gap to the
edge of the reference plane.
• Allow no more than 1/2 of a trace width to be routed over via antipad.
26. When routing the data lanes, route the outermost (that is, longest lane first) because this determines
the amount of trace length to add on the inner data lanes.
27. Are the clock pair assignments optimized to allow break-out of all pairs on a single critical layer?
28. The DDR2 data bus consists of 9 data byte lanes (assuming ECC is used). All signals within a given
byte lane should be routed on the same critical layer with the same via count.
Note: Some product implementations may only implement a 32-bit wide interface.
Byte Lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS
(0)
Byte Lane 1—MDQ(15:8), MDM(1), MDQS(1), MDQS
(1)
Byte Lane 2—MDQ(23:16), MDM(2), MDQS(2), MDQS
(2)
Byte Lane 3—MDQ(31:24), MDM(3), MDQS(3), MDQS
(3)
Byte Lane 4—MDQ(39:32), MDM(4), MDQS(4), MDQS
(4)
Byte Lane 5—MDQ(47:40), MDM(5), MDQS(5), MDQS
(5)
Byte Lane 6—MDQ(55:48), MDM(6), MDQS(6), MDQS
(6)
Byte Lane 7—MDQ(63:56), MDM(7), MDQS(7), MDQS
(7)
Byte Lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS
(8)
To facilitate fan-out of the DDR2 data lanes (if needed), alternate adjacent data lanes onto different
critical layers? See Figure 1 and Figure 2.
Note: If the device supports ECC, Freescale highly recommends that the user implement ECC on
the initial hardware prototypes.
29. DDR2 data group—Impedance range and spacing
• Single-ended target Impedance = 50–60 Ω range (MDQ, MDM)
• Differential target impedance = 100–120 Ω range (MDQS, MDQS
) Note: Some product
implementations may support only the single-ended version of the strobe.
• Referenced to a solid ground plane, thereby providing a low-impedance path for return currents.
• Trace space to other non-DDR2 data groups = 25 mil.
• Trace space requirements within the DDR2 data group = 10 mils (reducing to 7 mils inside the
DIMM area). Note: Based on a trace width of 5 mil.
30. Across all DDR2 data lanes, are all the data lanes matched to within 0.5 inch?
31. Is each data lane properly trace matched to within 20 mils of its respective differential data strobe?
(Assumes highest frequency operation.)
32. When adding trace lengths to any of the DDR2 signal groups, ensure that there is at least 25 mils
between serpentine loops that are in parallel.
Table 1. DDR2 Designer’s Checklist (continued)
Item Description Yes/No
数据线布线要求:
参考选实心地平面以提供
电流回流路径。
DDR和非DDR走线间距间隔
最低为25mils,在DDR内
部可以减少到10mils,在
DIMM(双列直插内存条)
区域可以减少到7mils
(线宽为5mils).
布线顺序:
1.数据线DQ、DM
2.地址&命令线Addr、Bank
Addr、RAS、CAS、WE
3.控制线CS、CKE、ODT
4.时钟线Clock_P/N
5.电源线
总体要求:
1.走线不能断裂
2.距离工作区边缘至少需
要30-40mils
3.和via电隔离区域至少
距离1/2线宽
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