ISP1581：经济型USB 2.0接口设备，支持高速通信与多功能应用

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ISP1581_w是一款专为低成本和高性能设计的Universal Serial Bus (USB) 2.0接口设备，它严格遵循USB 2.0规范，提供高速数据通信能力，适用于基于微控制器或微处理器的系统。这款产品的主要目标是实现便捷、兼容多类设备的连接，支持自动识别USB 2.0系统操作模式，并具备USB 1.1回退模式，确保在全速条件下仍能稳定运行。 ISP1581的核心特点是其通用串行总线接口，可以与系统的微控制器或处理器通过高速通用并行接口进行高效通信。这意味着它能够无缝集成到各种设备类别中，包括但不限于影像设备、大规模存储设备、通信设备、打印设备以及人类接口设备（HID）。这种灵活性使其具有广泛的适用性，无论是在工业控制、消费电子还是个人电脑领域都能找到应用场景。内部集成的通用直接内存访问（DMA）模块是另一个关键特性，它极大地简化了数据流应用的集成，提高了数据传输效率。该模块的不同配置针对大规模存储应用进行了优化，例如硬盘驱动器或固态硬盘，以实现快速读写和减少CPU的负载。采用模块化设计，ISP1581_w便于开发者根据具体项目需求进行定制和扩展，同时保持良好的兼容性和稳定性。此外，考虑到电源管理和热插拔功能，ISP1581_w还可能支持USB设备所需的电源管理和相应的安全措施，确保设备的可靠性和易用性。 ISP1581_w是一款强大的USB 2.0接口解决方案，集成了高性能通信、广泛兼容性、灵活配置和高效数据处理能力于一身，是现代电子设备中不可或缺的一部分，有助于简化系统设计，提高整体性能和用户体验。

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation Rev. 02 — 23 October 2000 12 of 73

9397 750 07648

DMA registers

DMA Command DMA controller 30 controls all DMA transfers 1

DMA Transfer Counter DMA controller 34 sets byte count for DMA Transfer 4

DMA Conﬁguration DMA controller 38 (byte 0) sets GDMA conﬁguration (counter enable,

burst length, data strobing, bus width)

39 (byte 1) sets ATA conﬁguration (IORDY enable,

mode selection: ATA/UDMA/MDMA/PIO)

DMA Hardware DMA controller 3C endian type, master/slave selection, signal

polarity for DACK, DREQ, DIOW, DIOR

1F0 Task File ATAPI peripheral 40 single address word register: byte 0 (lower

byte) is accessed ﬁrst

1F1Task File ATAPI peripheral 48 IDE device access 1

1F2 Task File ATAPI peripheral 49 IDE device access 1

1F3 Task File ATAPI peripheral 4A IDE device access 1

1F4 Task File ATAPI peripheral 4B IDE device access 1

1F5 Task File ATAPI peripheral 4C IDE device access 1

1F6 Task File ATAPI peripheral 4D IDE device access 1

1F7 Task File ATAPI peripheral 44 IDE device access (write only; reading

returns 00H)

3F6 Task File ATAPI peripheral 4E IDE device access 1

3F7 Task File ATAPI peripheral 4F IDE device access 1

DMA Interrupt Reason DMA controller 50 (byte 0) shows reason (source) for DMA interrupt 1

51 (byte 1) 1

DMA Interrupt Enable DMA controller 54 (byte 0) enables DMA interrupt sources 1

55 (byte 1) 1

DMA Endpoint DMA controller 58 selects endpoint FIFO, data ﬂow direction 1

DMA Strobe Timing DMA controller 60 strobe duration in UDMA/MDMA mode 1

General registers

Interrupt device 18 shows interrupt sources 4

Chip ID device 70 product ID code and hardware version 3

Frame Number device 74 last successfully received Start Of Frame:

lower byte (byte 0) is accessed ﬁrst

Scratch device 78 allows save/restore of ﬁrmware status

during ‘suspend’

Unlock Device device 7C re-enables register access after ‘suspend’ 2

Test Mode PHY 84 direct setting of D+, D− states, loopback

mode, internal transceiver test (PHY)

Table 4: Register summary

…continued

Name Destination Address

(Hex)

Description Size

(bytes)

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation Rev. 02 — 23 October 2000 14 of 73

9397 750 07648

9.2.2 Mode register (address: 0CH)

This register consists of 1 byte (bit allocation: see Tabl e 7). In 16-bit bus mode the

upper byte is ignored.

The Mode register controls the resume, suspend and wake-up behaviour, interrupt

activity, soft reset, clock signals and SoftConnect operation. This register also

controls the Power Off mode during ‘suspend’ state.

Table 7: Mode register: bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol CLKAON SNDRSU GOSUSP SFRESET GLINTENA WKUPCS PWROFF SOFTCT

Reset 00000000

Bus reset 0 0 0 0 unchanged 0 unchanged unchanged

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 8: Mode register: bit description

Bit Symbol Description

7 CLKAON Clock Always On: A logic 1 indicates that the internal clocks

are always running even during ‘suspend’ state. A logic 0

switches off the internal oscillator and PLL, when they are not

needed. During ‘suspend’ state, this bit must be set to logic 0 to

meet the suspend current requirements. The clock is stopped

after a delay of approximately 2 ms, following the setting of bit

GOSUSP.

6 SNDRSU Send Resume: Writing a logic 1 followed by a logic 0 will

generate an upstream ‘resume’ signal of 10 ms duration, after a

5 ms delay.

5 GOSUSP Go Suspend: Writing a logic 1 followed by a logic 0 will activate

‘suspend’ mode.

4 SFRESET Soft Reset: Writing a logic 1 followed by a logic 0 will enable a

software-initiated reset to ISP1581. A soft reset is similar to a

hardware-initiated reset (via the

RESET pin).

3 GLINTENA Global Interrupt Enable: A logic 1 enables all interrupts.

Individual interrupts can be masked OFF by clearing the

corresponding bits in the Interrupt Enable register. Bus reset

value: unchanged.

2 WKUPCS Wake-up on Chip Select: A logic 1 enables remote wake-up

via a LOW level on input

CS.

1 PWROFF Power Off mode: A logic 1 enables powering-off during

‘suspend’ state. Output SUSPEND is conﬁgured as a power

switch control signal for external devices (HIGH during

‘suspend’). Bus reset value: unchanged.

0 SOFTCT SoftConnect: A logic 1 enables the connection of the 1.5 kΩ

pull-up resistor on pin RPU to the D+ line. Bus reset value:

unchanged.

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation Rev. 02 — 23 October 2000 15 of 73

9397 750 07648

9.2.3 Interrupt Conﬁguration register (address: 10H)

This 1-byte register determines the behaviour and polarity of the INT output. The bit

allocation is shown in Tabl e 9. When the USB SIE receives or generates a ACK, NAK

or STALL, it will generate interrupts depending on three Debug mode bit ﬁelds:

•

CDBGMOD[1:0]: interrupts for the Control endpoint 0

•

DDBGMODIN[1:0]: interrupts for the DATA IN endpoints 1 to 7

•

DDBGMODOUT[1:0]: interrupts for the DATA OUT endpoints 1 to 7.

The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow

the user to individually conﬁgure when the ISP1581 will send an interrupt to the

external microprocessor. Table 11 lists the available combinations.

Bit INTPOL controls the signal polarity of the INT output (active HIGH or LOW, rising

or falling edge). For level-triggering bit INTLVL must be made logic 0. By setting

INTLVL to logic 1 an interrupt will generate a pulse of 60 ns (edge-triggering).

[1] First NAK: the ﬁrst NAK on an IN or OUT token after a previous ACK response.

Table 9: Interrupt Conﬁguration register: bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] INTLVL INTPOL

Reset 03H 03H 03H 0 0

Bus reset 03H 03H 03H unchanged unchanged

Access R/W R/W R/W R/W R/W

Table 10: Interrupt Conﬁguration register: bit description

Bit Symbol Description

7 to 6 CDBGMOD[1:0] Control 0 Debug Mode: values see Ta bl e 11

5 to 4 DDBGMODIN[1:0] Data Debug Mode IN: values see Tabl e 11

3 to 2 DDBGMODOUT[1:0] Data Debug Mode OUT: values see Table 1 1

1 INTLVL Interrupt Level: selects the signaling mode on output

INT (0 = level, 1 = pulsed). In pulsed mode an interrupt

produces a 60 ns pulse. Bus reset value: unchanged.

0 INTPOL Interrupt Polarity: selects signal polarity on output INT

(0 = active LOW, 1 = active HIGH). Bus reset value:

unchanged.

Table 11: Debug mode settings

Value CDBGMOD DDBGMODIN DDBGMODOUT

00H Interrupt on all ACK,

STALL and NAK

Interrupt on all ACK

and NAK

Interrupt on all ACK, STALL,

NYET and NAK

01H Interrupt on all ACK and

STALL

Interrupt on ACK Interrupt on ACK, STALL and

NYET

1XH Interrupt on all ACK,

STALL and ﬁrst NAK

[1]

Interrupt on all ACK

and ﬁrst NAK

[1]

Interrupt on all ACK, STALL,

NYET and ﬁrst NAK

[1]

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ISP1581：经济型USB 2.0接口设备，支持高速通信与多功能应用

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