Microsemi ProASIC3 Flash FPGA技术规格与优势

需积分: 9 60 浏览量更新于2024-07-12 收藏 6.33MB PDF 举报

"Actel公司的ProASIC3系列FPGA芯片技术文档，版本号为ds0097_v18，该文档着重介绍了该系列芯片的特性、优点以及相关的功能细节，包括其高容量、可重编程的闪存技术、高性能、低功耗以及高级I/O接口等特性。" Actel的ProASIC3系列FPGA（现场可编程门阵列）是一款集成了软核ARM支持的芯片，具有以下显著特点和优势： 1. **高容量**： - 提供了15,000至1,000,000个系统门的广泛选择，满足不同规模设计需求。 - 集成高达144Kbit的真双口SRAM，为高速缓存或数据存储提供充足空间。 - 提供多达300个用户I/O引脚，方便连接各种外部设备。 2. **可重编程的闪存技术**： - 采用130纳米7层金属（6铜）的闪存基CMOS工艺，实现高效能和低功耗。 - 支持即时启动Level 0功能，能在电源关闭时保留编程好的设计。 - 实现单芯片解决方案，减少了系统复杂性。 3. **高性能**： - 可实现350MHz的系统性能，适用于需要高速处理的应用。 - 支持3.3V、66MHz、64位PCI接口，符合工业标准，适合高性能接口需求。 4. **在系统编程（ISP）与安全性**： - 通过JTAG（遵循IEEE1532标准）提供ISP功能，除包含ARM的ProASIC3设备外，所有设备均支持。 - 内置128位高级加密标准（AES）解密，确保数据安全。 - FlashLock技术确保FPGA内容的安全，防止未授权访问。 5. **低功耗**： - 采用核心电压降低功耗，适用于低功耗系统。 - 支持1.5V电压系统，适应低电压环境。 - 采用低阻抗闪存开关，进一步减少功耗。 6. **高性能路由层次结构**： - 分段化的层次化路由和时钟结构，优化了信号传输速度和系统效率。 7. **高级I/O**： - 在A3P250及以上型号中，支持高达700Mbps的DDR和LVDS兼容I/O，实现高速数据传输。 - 支持1.5V、1.8V、2.5V和3.3V的混合电压操作，提高了灵活性。 - 按照JESD8-B标准，电源电压范围宽泛，允许I/O引脚在2.7V至3.6V之间工作，增强了系统的兼容性。这些特性使得Actel的ProASIC3系列FPGA适用于需要高性能、低功耗和高可靠性的应用，如通信、工业控制、军事和航空航天等领域。

ProASIC3 DC and Switching Characteristics

2-3 Revision 18

Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage.

Figure 2-1 • High-Temperature Data Retention (HTR)

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

Product

Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature T

STG

(°C)

Maximum Operating

Junction Temperature T

(°C)

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Table 2-4 • Overshoot and Undershoot Limits

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle

Maximum Overshoot/

Undershoot

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

100

110

70 85 100 105 110 115 120 125 130 135 140 145 150

Temperature (ºC)

Years

Tj (°C)

HTR

Lifetime

(yrs)

70 102.7

85 43.8

100 20.0

105 15.6

110 12.3

115 9.7

120 7.7

125 6.2

130 5.0

135 4.0

140 3.3

145 2.7

150 2.2

ProASIC3 Flash Family FPGAs

Revision 18 2-4

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC

3 device. These circuits ensure easy

transition from the powered-off state to the powered-up state of the device. The many different supplies can power up

in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2

on page 2-5.

There are five regions to consider during power-up.

ProASIC3 I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in

hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior.

Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC

activation level is specified as 1.1 V worst-case (see Figure 2-2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL

output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/Down Behavior of Low Power Flash

Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation.

Thermal Characteristics

Introduction

The temperature variable in the Microsemi Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the chip junction

to be higher than the ambient temperature.

EQ can be used to calculate junction temperature.

= Junction Temperature = T + T

where:

= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = 

* P



= Junction-to-ambient of the package. 

numbers are located in Table 2-5 on page 2-6.

P = Power dissipation

剩余220页未读，继续阅读

zhanying_109

粉丝: 0
资源: 5

Microsemi ProASIC3 Flash FPGA技术规格与优势

microsemi_proasic3_flash_family_fpgas_datasheet_ds-1592395.pdf

static_pll.rar_ProASIC3_pll vhdl

two_port_ram.rar_proasic3测试

周立功开发板ProASIC3实验-syn_FIFO代码

ACTEL ProASIC3 datasheet

ProASIC3实验文档.rar

RT ProASIC3：FPGA.pdf

ProASIC3系列芯片阅读手册.pdf

ProASIC3 StartKit开发板原理图-周立功

Actel ProASIC3 A3P030 FPGA数据手册详解

最新资源