STM32F7/H7系列Cortex-M7处理器编程手册

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"STM32_CM7系列微控制器的Cortex-M7处理器编程手册" STM32F7和STM32H7系列是基于Cortex-M7内核的高性能32位微控制器，专为微控制器市场设计。Cortex-M7处理器是Cortex-M家族中性能最高的成员，它结合了六级流水线的超标量结构，以及灵活的系统和内存接口，如AXI、AHB总线、缓存和紧密耦合的内存。这使得STM32F7和STM32H7系列在整数、浮点和数字信号处理（DSP）性能方面表现出色。 Cortex-M7处理器的一个关键特性是其双发能力，它可以同时执行负载/负载和负载/存储指令对到多个内存接口，显著提高了处理速度。此外，Cortex-M7保持了与现有Cortex-M处理器和工具的100%二进制兼容性，这意味着开发者可以利用已有的开发环境和库，无需进行大的修改，就能在Cortex-M7上工作。该编程手册详细介绍了STM32F7和STM32H7系列Cortex-M7处理器的编程模型，包括指令集和核心外设。编程模型提供了关于如何在处理器上编写和运行应用程序的基础，而指令集涵盖了所有可用的机器语言指令，这对于低级编程和优化至关重要。核心外设部分则涵盖了中断、定时器、串行通信接口、DMA等硬件模块的使用方法，这些是实现高效系统设计的关键组成部分。手册还可能涉及以下内容： 1. **内存管理**：详细说明了STM32F7和STM32H7系列的内存架构，包括闪存、SRAM的组织和访问方式，以及如何配置和使用缓存。 2. **中断和异常处理**：解释了中断和异常的工作机制，如何设置中断向量，以及如何处理中断服务例程。 3. **调试和仿真支持**：介绍了调试接口，如JTAG和SWD，以及如何使用这些接口进行程序调试和性能分析。 4. **电源管理**：描述了处理器的低功耗模式，以及如何有效地管理电源以延长电池寿命。 5. **外设互联**：详细阐述了如何通过AHB、APB总线连接和控制各种外设，以及AXI接口的使用。 6. **浮点运算单元（FPU）**：因为Cortex-M7内含FPU，手册会详细介绍浮点运算的使用，包括单精度和半精度浮点运算的支持。 7. **DSP扩展**：Cortex-M7处理器支持特定的DSP指令，手册会说明如何利用这些指令来提高数字信号处理应用的效率。 8. **实时操作系统（RTOS）集成**：提供关于如何将RTOS与Cortex-M7处理器集成的指导，以便于开发多任务应用。 9. **软件开发工具**：介绍推荐的IDE、编译器、调试器和其他开发工具，以及如何使用它们进行项目开发。这份STM32F7和STM32H7系列的Cortex-M7处理器编程手册是开发者深入理解和有效利用这些微控制器的宝贵资源，它涵盖了从基础到高级的所有重要概念和技术细节。

About this document PM0253

16/254 PM0253 Rev 5

order superscalar processor delivers exceptional power efficiency through an efficient

instruction set and extensively optimized design, providing high-end processing hardware

including IEEE754-compliant single-precision and double-precision floating-point

computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate

capabilities, saturating arithmetic and dedicated hardware division.

To facilitate the design of cost-sensitive devices, the Cortex

-M7 processor implements

tightly-coupled system components that reduce processor area while significantly improving

interrupt handling and system debug capabilities. The Cortex

-M7 processor implements a

version of the Thumb

instruction set based on Thumb-2 technology, ensuring high code

density and reduced program memory requirements. The Cortex

-M7 instruction set

provides the exceptional performance expected of a modern 32-bit architecture, with the

high code density of 8-bit and 16-bit microcontrollers.

The Cortex

-M7 processor closely integrates a configurable NVIC, to deliver industry-

leading interrupt performance. The NVIC includes a Non Maskable Interrupt (NMI), and

provides up to 256 interrupt priority levels. The tight integration of the processor core and

NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the

interrupt latency. This is achieved through the hardware stacking of registers, and the ability

to suspend load-multiple and store-multiple operations. Interrupt handlers do not require

wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain

optimization also significantly reduces the overhead when switching from one ISR to

another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to be rapidly powered down while still

retaining program state.

The reliability is increased with automatic fault detection and handling built-in. The

Cortex

-M7 processor uses ECC and SECDED on accesses to memory and has Memory

Build-in Self Test (MBIST) capability. The Cortex

-M7 processor is dual-redundant, which

means it can operate in lock-step. The MCU vendor determines the reliability features

configuration and therefore this can differ across different devices and families.

To increase instruction throughput, the Cortex

-M7 processor can execute certain pairs of

instructions simultaneously. This is called dual issue.

1.3.1 System level interface

The Cortex

-M7 processor provides multiple interfaces using AMBA

technology to provide

high speed, low latency memory accesses. It supports unaligned data accesses.

The Cortex

-M7 processor has an MPU that provides fine grain memory control, enabling

applications to utilize multiple privilege levels, separating and protecting code, data and

stack on a task-by-task basis. Such requirements are becoming critical in many embedded

applications such as automotive.

1.3.2 Integrated configurable debug

The Cortex

-M7 processor implements a complete hardware debug solution. This provides

high system visibility of the processor and memory through either a traditional JTAG port or

a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small

package devices. The MCU vendor determines the debug feature configuration and

therefore this can differ across different devices and families.

PM0253 Rev 5 17/254

PM0253 About this document

For system trace the processor integrates an Instrumentation Trace Macrocell (ITM)

together with data watchpoints and a profiling unit. To enable simple and cost-effective

profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a

stream of software-generated messages, data trace, and profiling information through a

single pin.

The optional CoreSight technology components, Embedded Trace Macrocell

™

(ETM),

delivers unrivalled instruction trace and data trace capture in an area far smaller than

traditional trace units, enabling many low cost MCUs to implement full instruction trace for

the first time.

The Breakpoint Unit provides up to eight hardware breakpoint comparators that debuggers

can use.

1.3.3 Cortex

-M7 processor features and benefits summary

• Tight integration of system peripherals reduces area and development costs.

• Thumb instruction set combines high code density with 32-bit performance.

• IEEE754-compliant single-precision and double-precision Floating-Point Unit (FPU).

• Power control optimization of system components.

• Integrated sleep modes for low-power consumption.

• Fast code execution permits slower processor clock or increases sleep mode time.

• Hardware division and fast digital-signal-processing orientated multiply accumulate.

• Saturating arithmetic for signal processing.

• Deterministic, high-performance interrupt handling for time-critical applications.

• MPU for safety-critical applications.

• Arm Cortex

-M7 with instruction cache and data cache

• Memory system features such as caches, Tightly-Coupled Memory (TCM) with DMA

port, and a high performance AXI external memory interface.

• Dedicated AHB slave (AHBS) interface for system access to TCMs

• Extensive debug and trace capabilities:

– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for

debugging, tracing, and code profiling.

1.3.4 Cortex

-M7 processor core peripherals

The Cortex

-M7 processor core peripherals are:

Nested Vectored Interrupt Controller

The NVIC is an embedded interrupt controller that supports low latency interrupt

processing.

System Control Block

The System Control Block (SCB) is the programmers model interface to the

processor. It provides system implementation information and system control,

including configuration, control, and reporting of system exceptions.

PM0253 Rev 5 19/254

PM0253 The Cortex-M7 processor

2 The Cortex-M7 processor

2.1 Programmers model

This section describes the Cortex

-M7 programmers model. In addition to the individual

core register descriptions, it contains information about the processor modes and privilege

levels for software execution and stacks.

2.1.1 Processor mode and privilege levels for software execution

The processor modes are:

The privilege levels for software execution are:

In Thread mode, the CONTROL register controls whether software execution is privileged or

unprivileged, see

CONTROL register on page 27. In Handler mode, software execution is

always privileged.

Only privileged software can write to the CONTROL register to change the privilege level for

software execution in Thread mode. Unprivileged software can use the

SVC instruction to

make a supervisor call to transfer control to privileged software.

2.1.2 Stacks

The processor uses a full descending stack. This means the stack pointer holds the address

of the last stacked item in memory. When the processor pushes a new item onto the stack, it

decrements the stack pointer and then writes the item to the new memory location. The

processor implements two stacks, the main stack and the process stack, with a pointer for

each held in independent registers, see

Stack pointer on page 21.

In Thread mode, the CONTROL register controls whether the processor uses the main

stack or the process stack, see

CONTROL register on page 27. In Handler mode, the

processor always uses the main stack. The options for processor operations are:

Thread mode Executes application software. The processor enters Thread mode

when it comes out of reset.

Handler mode Handles exceptions. The processor returns to Thread mode when it has

finished all exception processing.

Unprivileged The software:

• Has limited access to system registers using the

MSR

and

MRS

instructions, and cannot use the

CPS

instruction to mask interrupts.

• Cannot access the system timer, NVIC, or system control block.

• Might have restricted access to memory or peripherals.

Unprivileged software executes at the unprivileged level.

Privileged The software can use all the instructions and has access to all

resources.

Privileged software executes at the privileged level.

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STM32F7/H7系列Cortex-M7处理器编程手册

IEC60730B_CM7_3_0_DOC.zip

stm32 SVD文件合集

stm32h750.h中无法打开core_cm7.h文件

STM32H747I_DISCO_CM7\Exe\STM32H747I_DISCO_CM7.axf: error: L6047U: The size of this image (330564 bytes) exceeds the maximum allowed for this version of the linker

Load "STM32H747I_DISCO_CM7\\Exe\\STM32H747I_DISCO_CM7.axf" No Algorithm found for: 08000000H - 080015E3H Erase skipped! Error: Flash Download failed - "Cortex-M7" Flash Load finished at 20:35:04

可以通过修改代码来减少运行空间以消除下面的错误：STM32H747I_DISCO_CM7\Exe\STM32H747I_DISCO_CM7.axf: error: L6047U: The size of this image (329224 bytes) exceeds the maximum allowed for this version of the linker

Note: source file '../CM7/Src/main.c' - object file renamed from 'STM32H747I_DISCO_CM7\Exe\main.o' to 'STM32H747I_DISCO_CM7\Exe\main_1.o'.

RT1170_RM.pdf

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