没有合适的资源?快使用搜索试试~ 我知道了~
首页TMS320F2837xD中文手册:C2000软件与系统控制详解
TMS320F2837xD中文手册是一本专注于TI公司C2000系列DSP28377微控制器的详细技术参考手册,对于深入理解并学习该型号的数字信号处理器(DSP)具有极高的价值。手册发布于2014年8月至2019年9月,覆盖了丰富的技术内容,旨在帮助用户掌握硬件设计、软件支持和系统控制的关键要点。
1. **C2000软件支持**:
- 章节1介绍了C2000系列软件的基础,包括C2000Ware的结构,它是TI为C28x处理器提供的软件开发环境,包含编译器、调试器等工具。
- 文档部分详细讲述了如何获取和使用相关的开发文档,以便开发者了解设备的特性和编程接口。
- 设备章节列出了TMS320F2837x支持的多种功能,如浮点处理单元(FPU)、三角函数数学单元以及Viterbi、复数数学和CRC单元(VCU-II),这些都是进行高性能信号处理必不可少的硬件特性。
2. **C28x处理器**:
- 介绍部分概述了处理器的核心功能,包括其特点,如高处理能力、低功耗以及适用于工业控制、通信系统等领域。
- 特别关注了处理器的数学运算能力,如FPU用于高效执行实数和复数运算,而VCU-II则提供了高级数学和通信算法的支持。
3. **系统控制**:
- 这一章着重讲解了设备的系统控制功能,如设备标识、配置寄存器管理,以及各种类型的复位机制。
- 外部reset(XRS)允许外部信号触发重启,而POR(电源-on reset)在上电时初始化系统。此外,还有用于调试的Debugger Reset (SYSRS)、防止程序死锁的Watchdog Reset (WDRS)、以及安全代码复制复位(SCCRESET)等功能。
- Hibernate Reset (HIBRESET)则是针对节能设计的一种特殊模式,使设备进入休眠状态以降低功耗。
通过阅读这本手册,学习者能够全面掌握TMS320F2837x DSP28377的硬件特性、软件开发流程以及系统级控制方法,这对于从事嵌入式系统设计、信号处理或控制系统开发的工程师来说是一本不可或缺的参考资料。无论是硬件配置、软件编写还是故障排查,这份文档都提供了详尽且实用的指导。
www.ti.com
16
SPRUHX5G–August 2014–Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
23.2 Configuring Device Pins................................................................................................ 2530
23.3 Functional Description .................................................................................................. 2530
23.3.1 Functional Block Diagram.................................................................................... 2530
23.3.2 Data Flow ...................................................................................................... 2530
23.3.3 Clock Generation and Control ............................................................................... 2531
23.4 IO Interface and System Requirements.............................................................................. 2533
23.4.1 Pin Multiplexing................................................................................................ 2533
23.4.2 Internal DMA Controller Description ........................................................................ 2533
23.4.3 Protocol Description .......................................................................................... 2535
23.4.4 Data Format.................................................................................................... 2538
23.4.5 Reset Considerations......................................................................................... 2538
23.4.6 Interrupt Support .............................................................................................. 2539
23.4.7 Emulation Considerations .................................................................................... 2540
23.4.8 Transmit and Receive FIFOs ................................................................................ 2540
23.4.9 Transmit and Receive Data (MSG) RAM .................................................................. 2540
23.4.10 Initialization and Operation ................................................................................. 2541
23.5 UPP Registers ........................................................................................................... 2543
23.5.1 UPP Base Addresses......................................................................................... 2543
23.5.2 UPP_REGS Registers........................................................................................ 2544
24 External Memory Interface (EMIF) ..................................................................................... 2579
24.1 Introduction............................................................................................................... 2580
24.1.1 Purpose of the Peripheral .................................................................................... 2580
24.2 Features .................................................................................................................. 2581
24.2.1 Asynchronous Memory Support............................................................................. 2581
24.2.2 Synchronous DRAM Memory Support ..................................................................... 2581
24.3 Functional Block Diagram.............................................................................................. 2581
24.4 Configuring Device Pins................................................................................................ 2582
24.5 EMIF Module Architecture ............................................................................................. 2582
24.5.1 EMIF Clock Control ........................................................................................... 2582
24.5.2 EMIF Requests ................................................................................................ 2582
24.5.3 EMIF Signal Descriptions .................................................................................... 2583
24.5.4 EMIF Signal Multiplexing Control ........................................................................... 2584
24.5.5 SDRAM Controller and Interface............................................................................ 2584
24.5.6 Asynchronous Controller and Interface .................................................................... 2597
24.5.7 Data Bus Parking.............................................................................................. 2609
24.5.8 Reset and Initialization Considerations..................................................................... 2609
24.5.9 Interrupt Support .............................................................................................. 2609
24.5.10 DMA Event Support ......................................................................................... 2610
24.5.11 EMIF Signal Multiplexing ................................................................................... 2610
24.5.12 Memory Map ................................................................................................. 2610
24.5.13 Priority and Arbitration ...................................................................................... 2611
24.5.14 System Considerations ..................................................................................... 2612
24.5.15 Power Management ......................................................................................... 2613
24.5.16 Emulation Considerations .................................................................................. 2613
24.6 Example Configuration ................................................................................................. 2614
24.6.1 Hardware Interface............................................................................................ 2614
24.6.2 Software Configuration ....................................................................................... 2614
24.7 EMIF Registers .......................................................................................................... 2622
24.7.1 EMIF Base Addresses........................................................................................ 2622
24.7.2 EMIF_REGS Registers ....................................................................................... 2623
24.7.3 EMIF1_CONFIG_REGS Registers ......................................................................... 2643
24.7.4 Register to Driverlib Function Mapping..................................................................... 2647
25 Configurable Logic Block (CLB)........................................................................................ 2648
www.ti.com
17
SPRUHX5G–August 2014–Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
Contents
25.1 Introduction............................................................................................................... 2649
25.2 Features .................................................................................................................. 2649
25.3 CLB Input/Output Connection ......................................................................................... 2650
25.3.1 Overview ....................................................................................................... 2650
25.3.2 CLB Input Selection........................................................................................... 2650
25.3.3 CLB Output Selection......................................................................................... 2654
25.3.4 Peripheral Signal Multiplexer ............................................................................... 2655
25.4 The CLB Tile............................................................................................................. 2657
25.4.1 Static Switch Block ........................................................................................... 2658
25.4.2 Counter Block.................................................................................................. 2660
25.4.3 FSM Block...................................................................................................... 2662
25.4.4 LUT4 Block..................................................................................................... 2663
25.4.5 Output LUT Block ............................................................................................. 2663
25.4.6 High Level Controller (HLC) ................................................................................. 2664
25.5 CPU Interface............................................................................................................ 2667
25.5.1 Register Description .......................................................................................... 2667
25.5.2 Non-Memory Mapped Registers ............................................................................ 2668
25.6 CLB Registers ........................................................................................................... 2669
25.6.1 CLB Base Addresses ......................................................................................... 2669
25.6.2 CLB_LOGIC_CONFIG_REGS Registers .................................................................. 2670
25.6.3 CLB_LOGIC_CONTROL_REGS Registers................................................................ 2703
25.6.4 CLB_DATA_EXCHANGE_REGS Registers............................................................... 2730
25.6.5 CLB_DATA_EXCHANGE_REGS Registers............................................................... 2733
25.6.6 Register to Driverlib Function Mapping..................................................................... 2736
Revision History ...................................................................................................................... 2739
www.ti.com
18
SPRUHX5G–August 2014–Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
List of Figures
3-1. Device Interrupt Architecture ............................................................................................. 92
3-2. Interrupt Propagation Path ................................................................................................ 93
3-3. Missing Clock Detection Logic .......................................................................................... 106
3-4. ERRORSTS Pin Diagram ............................................................................................... 107
3-5. Clocking System .......................................................................................................... 108
3-6. Single-ended 3.3V External Clock...................................................................................... 109
3-7. External Crystal ........................................................................................................... 109
3-8. External Resonator ....................................................................................................... 110
3-9. AUXCLKIN................................................................................................................. 110
3-10. CPU-Timers ............................................................................................................... 117
3-11. CPU-Timer Interrupts Signals and Output Signal .................................................................... 118
3-12. CPU Watchdog Timer Module ......................................................................................... 119
3-13. Memory Architecture ..................................................................................................... 125
3-14. Arbitration Scheme on Global Shared Memories..................................................................... 127
3-15. Arbitration Scheme on Local Shared Memories ...................................................................... 127
3-16. FMC Interface with Core, Bank and Pump ............................................................................ 134
3-17. Flash Prefetch Mode ..................................................................................................... 137
3-18. ECC Logic Inputs and Outputs.......................................................................................... 140
3-19. PUMP_OWNERSHIP Configuration ................................................................................... 144
3-20. Storage of Zone-Select Bits in OTP ................................................................................... 148
3-21. Location of Zone-Select Block Based on Link-Pointer............................................................... 149
3-22. CSM Password Match Flow (PMF)..................................................................................... 153
3-23. ECSL Password Match Flow (PMF).................................................................................... 155
3-24. TIM Register............................................................................................................... 160
3-25. PRD Register.............................................................................................................. 161
3-26. TCR Register.............................................................................................................. 162
3-27. TPR Register .............................................................................................................. 164
3-28. TPRH Register ............................................................................................................ 165
3-29. PIECTRL Register ........................................................................................................ 168
3-30. PIEACK Register.......................................................................................................... 169
3-31. PIEIER1 Register ......................................................................................................... 170
3-32. PIEIFR1 Register ......................................................................................................... 172
3-33. PIEIER2 Register ......................................................................................................... 174
3-34. PIEIFR2 Register ......................................................................................................... 176
3-35. PIEIER3 Register ......................................................................................................... 178
3-36. PIEIFR3 Register ......................................................................................................... 180
3-37. PIEIER4 Register ......................................................................................................... 182
3-38. PIEIFR4 Register ......................................................................................................... 184
3-39. PIEIER5 Register ......................................................................................................... 186
3-40. PIEIFR5 Register ......................................................................................................... 188
3-41. PIEIER6 Register ......................................................................................................... 190
3-42. PIEIFR6 Register ......................................................................................................... 192
3-43. PIEIER7 Register ......................................................................................................... 194
3-44. PIEIFR7 Register ......................................................................................................... 196
3-45. PIEIER8 Register ......................................................................................................... 198
3-46. PIEIFR8 Register ......................................................................................................... 200
3-47. PIEIER9 Register ......................................................................................................... 202
www.ti.com
19
SPRUHX5G–August 2014–Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
3-48. PIEIFR9 Register ......................................................................................................... 204
3-49. PIEIER10 Register........................................................................................................ 206
3-50. PIEIFR10 Register........................................................................................................ 208
3-51. PIEIER11 Register........................................................................................................ 210
3-52. PIEIFR11 Register........................................................................................................ 212
3-53. PIEIER12 Register........................................................................................................ 214
3-54. PIEIFR12 Register........................................................................................................ 216
3-55. SCSR Register............................................................................................................ 219
3-56. WDCNTR Register ....................................................................................................... 220
3-57. WDKEY Register.......................................................................................................... 221
3-58. WDCR Register ........................................................................................................... 222
3-59. WDWCR Register ........................................................................................................ 223
3-60. NMICFG Register......................................................................................................... 225
3-61. NMIFLG Register ......................................................................................................... 226
3-62. NMIFLGCLR Register.................................................................................................... 228
3-63. NMIFLGFRC Register.................................................................................................... 230
3-64. NMIWDCNT Register .................................................................................................... 231
3-65. NMIWDPRD Register .................................................................................................... 232
3-66. NMISHDFLG Register.................................................................................................... 233
3-67. XINT1CR Register........................................................................................................ 236
3-68. XINT2CR Register........................................................................................................ 237
3-69. XINT3CR Register........................................................................................................ 238
3-70. XINT4CR Register........................................................................................................ 239
3-71. XINT5CR Register........................................................................................................ 240
3-72. XINT1CTR Register ...................................................................................................... 241
3-73. XINT2CTR Register ...................................................................................................... 242
3-74. XINT3CTR Register ...................................................................................................... 243
3-75. CLA1TASKSRCSELLOCK Register ................................................................................... 245
3-76. DMACHSRCSELLOCK Register ....................................................................................... 246
3-77. CLA1TASKSRCSEL1 Register ......................................................................................... 247
3-78. CLA1TASKSRCSEL2 Register ......................................................................................... 248
3-79. DMACHSRCSEL1 Register ............................................................................................. 249
3-80. DMACHSRCSEL2 Register ............................................................................................. 250
3-81. PARTIDL Register ........................................................................................................ 253
3-82. PARTIDH Register........................................................................................................ 255
3-83. REVID Register ........................................................................................................... 256
3-84. DC0 Register .............................................................................................................. 257
3-85. DC1 Register .............................................................................................................. 258
3-86. DC2 Register .............................................................................................................. 259
3-87. DC3 Register .............................................................................................................. 260
3-88. DC4 Register .............................................................................................................. 262
3-89. DC5 Register .............................................................................................................. 263
3-90. DC6 Register .............................................................................................................. 264
3-91. DC7 Register .............................................................................................................. 265
3-92. DC8 Register .............................................................................................................. 266
3-93. DC9 Register .............................................................................................................. 267
3-94. DC10 Register............................................................................................................. 268
3-95. DC11 Register............................................................................................................. 269
3-96. DC12 Register............................................................................................................. 270
www.ti.com
20
SPRUHX5G–August 2014–Revised September 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
3-97. DC13 Register............................................................................................................. 271
3-98. DC14 Register............................................................................................................. 272
3-99. DC15 Register............................................................................................................. 273
3-100. DC17 Register............................................................................................................. 275
3-101. DC18 Register............................................................................................................. 276
3-102. DC20 Register............................................................................................................. 277
3-103. PERCNF1 Register....................................................................................................... 279
3-104. FUSEERR Register....................................................................................................... 280
3-105. SOFTPRES0 Register ................................................................................................... 281
3-106. SOFTPRES1 Register ................................................................................................... 282
3-107. SOFTPRES2 Register ................................................................................................... 283
3-108. SOFTPRES3 Register ................................................................................................... 285
3-109. SOFTPRES4 Register ................................................................................................... 286
3-110. SOFTPRES6 Register ................................................................................................... 287
3-111. SOFTPRES7 Register ................................................................................................... 288
3-112. SOFTPRES8 Register ................................................................................................... 289
3-113. SOFTPRES9 Register ................................................................................................... 290
3-114. SOFTPRES11 Register .................................................................................................. 291
3-115. SOFTPRES13 Register .................................................................................................. 292
3-116. SOFTPRES14 Register .................................................................................................. 293
3-117. SOFTPRES16 Register .................................................................................................. 294
3-118. SYSDBGCTL Register ................................................................................................... 295
3-119. CLKCFGLOCK1 Register................................................................................................ 298
3-120. CLKSRCCTL1 Register .................................................................................................. 300
3-121. CLKSRCCTL2 Register .................................................................................................. 302
3-122. CLKSRCCTL3 Register .................................................................................................. 304
3-123. SYSPLLCTL1 Register................................................................................................... 305
3-124. SYSPLLMULT Register .................................................................................................. 306
3-125. SYSPLLSTS Register .................................................................................................... 307
3-126. AUXPLLCTL1 Register .................................................................................................. 308
3-127. AUXPLLMULT Register.................................................................................................. 309
3-128. AUXPLLSTS Register.................................................................................................... 310
3-129. SYSCLKDIVSEL Register ............................................................................................... 311
3-130. AUXCLKDIVSEL Register ............................................................................................... 312
3-131. PERCLKDIVSEL Register ............................................................................................... 313
3-132. XCLKOUTDIVSEL Register ............................................................................................. 314
3-133. LOSPCP Register ........................................................................................................ 315
3-134. MCDCR Register ......................................................................................................... 316
3-135. X1CNT Register........................................................................................................... 317
3-136. CPUSYSLOCK1 Register ............................................................................................... 320
3-137. HIBBOOTMODE Register ............................................................................................... 323
3-138. IORESTOREADDR Register ............................................................................................ 324
3-139. PIEVERRADDR Register ................................................................................................ 325
3-140. PCLKCR0 Register ....................................................................................................... 326
3-141. PCLKCR1 Register ....................................................................................................... 328
3-142. PCLKCR2 Register ....................................................................................................... 329
3-143. PCLKCR3 Register ....................................................................................................... 331
3-144. PCLKCR4 Register ....................................................................................................... 333
3-145. PCLKCR6 Register ....................................................................................................... 334
剩余2739页未读,继续阅读
2020-04-27 上传
2020-04-27 上传
2020-04-27 上传
2020-04-27 上传
2020-04-27 上传
189 浏览量
点击了解资源详情
胡肖飞
- 粉丝: 0
- 资源: 3
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- Java集合ArrayList实现字符串管理及效果展示
- 实现2D3D相机拾取射线的关键技术
- LiveLy-公寓管理门户:创新体验与技术实现
- 易语言打造的快捷禁止程序运行小工具
- Microgateway核心:实现配置和插件的主端口转发
- 掌握Java基本操作:增删查改入门代码详解
- Apache Tomcat 7.0.109 Windows版下载指南
- Qt实现文件系统浏览器界面设计与功能开发
- ReactJS新手实验:搭建与运行教程
- 探索生成艺术:几个月创意Processing实验
- Django框架下Cisco IOx平台实战开发案例源码解析
- 在Linux环境下配置Java版VTK开发环境
- 29街网上城市公司网站系统v1.0:企业建站全面解决方案
- WordPress CMB2插件的Suggest字段类型使用教程
- TCP协议实现的Java桌面聊天客户端应用
- ANR-WatchDog: 检测Android应用无响应并报告异常
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功