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16
SPRUHX5G–August 2014–Revised September 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
Contents
23.2 Configuring Device Pins................................................................................................ 2530
23.3 Functional Description .................................................................................................. 2530
23.3.1 Functional Block Diagram.................................................................................... 2530
23.3.2 Data Flow ...................................................................................................... 2530
23.3.3 Clock Generation and Control ............................................................................... 2531
23.4 IO Interface and System Requirements.............................................................................. 2533
23.4.1 Pin Multiplexing................................................................................................ 2533
23.4.2 Internal DMA Controller Description ........................................................................ 2533
23.4.3 Protocol Description .......................................................................................... 2535
23.4.4 Data Format.................................................................................................... 2538
23.4.5 Reset Considerations......................................................................................... 2538
23.4.6 Interrupt Support .............................................................................................. 2539
23.4.7 Emulation Considerations .................................................................................... 2540
23.4.8 Transmit and Receive FIFOs ................................................................................ 2540
23.4.9 Transmit and Receive Data (MSG) RAM .................................................................. 2540
23.4.10 Initialization and Operation ................................................................................. 2541
23.5 UPP Registers ........................................................................................................... 2543
23.5.1 UPP Base Addresses......................................................................................... 2543
23.5.2 UPP_REGS Registers........................................................................................ 2544
24 External Memory Interface (EMIF) ..................................................................................... 2579
24.1 Introduction............................................................................................................... 2580
24.1.1 Purpose of the Peripheral .................................................................................... 2580
24.2 Features .................................................................................................................. 2581
24.2.1 Asynchronous Memory Support............................................................................. 2581
24.2.2 Synchronous DRAM Memory Support ..................................................................... 2581
24.3 Functional Block Diagram.............................................................................................. 2581
24.4 Configuring Device Pins................................................................................................ 2582
24.5 EMIF Module Architecture ............................................................................................. 2582
24.5.1 EMIF Clock Control ........................................................................................... 2582
24.5.2 EMIF Requests ................................................................................................ 2582
24.5.3 EMIF Signal Descriptions .................................................................................... 2583
24.5.4 EMIF Signal Multiplexing Control ........................................................................... 2584
24.5.5 SDRAM Controller and Interface............................................................................ 2584
24.5.6 Asynchronous Controller and Interface .................................................................... 2597
24.5.7 Data Bus Parking.............................................................................................. 2609
24.5.8 Reset and Initialization Considerations..................................................................... 2609
24.5.9 Interrupt Support .............................................................................................. 2609
24.5.10 DMA Event Support ......................................................................................... 2610
24.5.11 EMIF Signal Multiplexing ................................................................................... 2610
24.5.12 Memory Map ................................................................................................. 2610
24.5.13 Priority and Arbitration ...................................................................................... 2611
24.5.14 System Considerations ..................................................................................... 2612
24.5.15 Power Management ......................................................................................... 2613
24.5.16 Emulation Considerations .................................................................................. 2613
24.6 Example Configuration ................................................................................................. 2614
24.6.1 Hardware Interface............................................................................................ 2614
24.6.2 Software Configuration ....................................................................................... 2614
24.7 EMIF Registers .......................................................................................................... 2622
24.7.1 EMIF Base Addresses........................................................................................ 2622
24.7.2 EMIF_REGS Registers ....................................................................................... 2623
24.7.3 EMIF1_CONFIG_REGS Registers ......................................................................... 2643
24.7.4 Register to Driverlib Function Mapping..................................................................... 2647
25 Configurable Logic Block (CLB)........................................................................................ 2648