MPC5125微控制器参考手册：BSP驱动编程指南

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"MPC5125用户手册是关于Freescale Semiconductor的MPC5125微控制器的参考手册，版本为Rev3，发布于2011年10月。该手册提供了BSP驱动编程的信息，方便查询与接口驱动相关的寄存器。主要涉及的标签是MPC底层寄存器。" MPC5125是一款微控制器，其功能丰富，广泛应用于各种嵌入式系统。以下是对MPC5125关键模块和特性的详细说明： 1. **e300处理器核心**: MPC5125基于e300处理器内核，这是一个高效的RISC架构，提供高性能计算能力，适合实时操作系统。 2. **显示接口单元(DIU)**: DIU允许MPC5125与各种显示器进行通信，如LCD、CRT等，支持图形和文本显示。 3. **USB控制器**: 内置的USB控制器支持USB设备和主机模式，可用于数据传输和外设连接。 4. **直接内存访问(DMA)控制器**: DMA控制器可以提高数据传输效率，允许在不占用CPU资源的情况下进行内存和外设之间的大容量数据传输。 5. **DDR SDRAM内存控制器**: 提供对DDR SDRAM内存的支持，实现高速数据存取，增强系统的内存性能。 6. **32KB片上SRAM**: 为系统提供快速且低延迟的内部存储空间，用于缓存和临时数据存储。 7. **快速以太网控制器(FEC)**: 实现10/100Mbps以太网连接，支持网络通信。 8. **NAND闪存接口**: 提供与NAND闪存设备的接口，用于存储大量非易失性数据。 9. **本地加总总线(LPC)接口**: 允许与使用LPC标准的外设（如串行EEPROM、实时时钟等）进行通信。 10. **安全数字主机控制器(SDHC)**: 支持SD和MMC卡，适用于扩展存储和多媒体应用。 11. **控制器区域网络(CAN)**: 集成CAN控制器，符合CAN 2.0B协议，用于汽车和其他工业自动化系统中的网络通信。 12. **集成电路通信(I2C)**: 提供I2C接口，可连接多种I2C兼容的传感器和外设。 13. **可编程串行控制器(PSC)**: PSC可以配置为UART、SPI或I2C，支持多种串行通信协议。 14. **J1850字节数据链路控制器(BDLC)接口**: 专为汽车应用设计，如汽车网络通信。 15. **通用输入/输出(GPIO)**: 提供灵活的GPIO引脚，可以配置为输入或输出，以连接各种外部设备。 16. **片上实时钟(RTC)**: 内置RTC确保即使在主电源关闭时也能保持准确的时间。 17. **集成电路识别模块(IIM)**: 用于读取和验证微控制器的固件和配置信息。 18. **片上温度传感器**: 监测微控制器及其环境的温度，有助于系统健康管理。 19. **电源模式**: 提供多种电源管理模式，以优化能效和延长电池寿命。 20. **系统定时器**: 提供精确的定时功能，用于计时、中断触发和其他系统级任务。了解这些特性后，开发者可以根据需求利用MPC5125的BSP驱动程序来实现特定的功能，比如网络通信、存储扩展、设备控制等。手册中的寄存器信息对于理解如何直接操作硬件至关重要，是编写高效且可靠的驱动程序的基础。

MPC5125 Microcontroller Reference Manual, Rev 3

xiv Freescale Confidential Proprietary, NDA Required Freescale Semiconductor

MPC5125 Microcontroller Reference Manual, Rev 3

Freescale Confidential Proprietary, NDA Required xvFreescale Semiconductor

About this book

This reference manual describes the MPC5125 microcontroller family for software and hardware

developers. Information regarding bus timing, signal behavior, and AC, DC, and thermal characteristics

are detailed in the device data sheet (MPC5125 Data Sheet).

The information in this book is subject to change without notice, as described in the disclaimers on the title

page. As with any technical documentation, the reader needs to make sure to use the most recent version

of the documentation.

To locate any published errata or updates for this document, visit the Freescale web site at

http://www.freescale.com/.

Audience

This manual is intended for system software and hardware developers and applications programmers who

want to develop products with the MPC5125 microcontroller family. It is assumed that the reader

understands operating systems, microprocessor system design, basic principles of software and hardware,

and basic details of the Power architecture.

Organization

Following is a summary and brief description of the major sections of this manual:

• Chapter 1, “Overview,” includes general descriptions of the modules and features incorporated in

the device while focusing on new features.

• Chapter 2, “System Configuration and Memory Map (XLBMEN + Mem Map),” describes the

memory map and configuration for the MPC5125.

• Chapter 3, “Signal Descriptions,” summarizes the external signal functions, their static electrical

characteristics, and pad configuration settings for the MPC5125.

• Chapter 4, “Reset,” describes the reset sources available on the MPC5125, including details on

status flags and default configurations.

• Chapter 5, “Clocks and Low-Power Modes,” describes the various clock sources that are available

on the MPC5125 device.

• Chapter 6, “Byte Data Link Controller (BDLC),” describes the BDLC, which is a Society of

Automotive Engineers (SAE) J1850-compatible serial network communication module.

• Chapter 7, “CPU e300 Core Power Architecture,” describes the organization of the Power

processor core on the MPC5125, and gives an overview of the programming models as they are

implemented on the device.

• Chapter 8, “CSB Arbiter and Bus Monitor,” describes the Coherent Systems Bus (CSB) arbiter and

its configuration, control, and status registers.

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Freescale Confidential Proprietary, NDA Required xviFreescale Semiconductor

• Chapter 9, “Direct Memory Access (DMA),” describes the DMA controller implemented on the

MPC5125.

• Chapter 10, “Display Interface Unit (DIU),” describes the Display Interface Unit (DIU)

implemented on the MPC5125.

• Chapter 11, “DRAM Controller,” describes the multi-port DRAM controller that supports

Mobile-DDR, DDR-1, DDR-2, and SDR memories.

• Chapter 12, “Multi-port DRAM Controller Priority Manager,” describes the priority manager for

the DRAM controller.

• Chapter 13, “External Memory Bus (EMB),” describes how the LPC and the NFC share the

External Memory Bus.

• Chapter 14, “Fast Ethernet Controller (FEC),” describes the feature set, operation, and

programming model of the FEC block.

• Chapter 15, “General Purpose Timers (GPT),” describes eight independent timer channels that

perform general purpose timer and general purpose I/O (GPIO) functions.

• Chapter 16, “General Purpose I/O (GPIO),” describes the general purpose I/O module, including

pin descriptions, register settings and interrupt capabilities.

• Chapter 17, “Integrated Programmable Interrupt Controller (IPIC),” summarizes the software and

hardware interrupts for the MPC5125 device.

• Chapter 18, “IIM/Fusebox,” describes the module that provides an interface for reading and

programming information stored in on-chip fuse elements.

• Chapter 19, “Inter-Integrated Circuit (I2C),” describes the I

C module, including I

C protocol,

clock synchronization, and I

C programming model registers.

• Chapter 20, “I/O Control,” describes the controls for the functional muxing and configuration of

the pads.

• Chapter 21, “LocalPlus Bus Controller (LPC),” describes the external bus interface of the

MPC5125.

• Chapter 22, “MSCAN,” describes the CAN module, a communication controller implementing the

CAN protocol according to Bosch Specification version 2.0B.

• Chapter 23, “NAND Flash Controller (NFC),” describes the interface to standard NAND flash

memory devices.

• Chapter 24, “Power Management Control Module (PMC),” describes the power blocks that

provide voltage control for the internal logic of the device.

• Chapter 25, “Programmable Serial Controller (PSC),” describes the UART, AC97, Codec, and I

modes.

• Chapter 26, “PSC Centralized FIFO Controller (FIFOC),” describes the centralized FIFO

controller for the PSC modules.

• Chapter 27, “Real Time Clock (RTC),” describes the real time clock.

• Chapter 28, “Secure Digital Host Controller (SDHC),” describes the module that interfaces to

Multimedia Cards (MMC), Secure Digital (SD) memory cards, and I/O cards.

• Chapter 29, “Software Watchdog Timer (WDT),” describes the counter that guards against

software errors by periodically issuing a reset unless interrupted by software.

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• Chapter 30, “SRAM Memory (MEM),” describes the on-chip static RAM (SRAM)

implementation.

• Chapter 31, “Temperature Sensor,” describes the module that monitors the internal temperature of

the MPC5125.

• Chapter 32, “Universal Serial Bus Interface with On-The-Go,” describes the universal serial bus

(USB) interface on the MPC5125.

• Appendix A, “Memory Map,” provides a detailed listing of the memory-mapped registers for the

MPC5125.

Suggested reading

This section lists additional reading that provides background for the information in this manual as well as

general information about PowerPC architecture.

General information

Useful information about the PowerPC architecture and computer architecture in general:

• Programming Environments Manual for 32-Bit Implementations of the PowerPC™ Architecture

(MPCFPE32B)

• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross

Bannatyne, Joseph D. Greenfield

• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David

A. Patterson.

• Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A.

Patterson and John L. Hennessy.

PowerPC documentation

PowerPC documentation is available from the sources listed on the back cover of this manual, as well as

http://www.freescale.com/powerarchitecture .

• Reference manuals (formerly called user’s manuals)—These books provide details about

individual PowerPC implementations and are intended to be used in conjunction with the PowerPC

Programmers Reference Manual.

• Addenda/errata to reference manuals—Because some processors have follow-on parts, an

addendum is provided that describes the additional features and functionality changes. Also, if

mistakes are found within a reference manual, an errata document will be issued before the next

published release of the reference manual. These addenda/errata are intended for use with the

corresponding reference manuals.

• Data sheets—Data sheets provide specific information regarding pin-out diagrams, bus timing,

signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations.

• Product briefs—Each device has a product brief that provides an overview of its features. This

document is roughly equivalent to the overview (Chapter 1) of a device’s reference manual.

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Freescale Confidential Proprietary, NDA Required xviiiFreescale Semiconductor

• Application notes—These short documents address specific design issues useful to programmers

and engineers working with Freescale Semiconductor processors.

Additional literature is published as new processors become available. For a current list of PowerPC

documentation, refer to http://www.freescale.com/powerarchitecture .

Conventions

This document uses the following notational conventions:

cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value of

one, it is said to be set.

reserved When a bit or address is reserved, it should not be written. If read, its value is

cannot be not guaranteed. Reading or writing to reserved bits or addresses may

cause unexpected results.

MNEMONICS In text, instruction mnemonics are shown in uppercase.

mnemonics In code and tables, instruction mnemonics are shown in lowercase.

italics Italics indicate variable command parameters.

Book titles in text are set in italics.

0b0 Prefix to denote binary number (e.g., 0b0110_0111)

0x0 Prefix to denote hexadecimal number (e.g., 0xFFF0_FFFC)

b Suffix to denote binary number (e.g., 0110_0111b)

d Suffix to denote decimal number (e.g., 12345d)

h Suffix to denote hexadecimal number (e.g., FFF0_FFFCh)

REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges

appear in brackets. For example, RAMBAR[BA] identifies the base address field

in the RAM base address register.

nibble A 4-bit data unit

byte An 8-bit data unit

halfword A 16-bit data unit

word A 32-bit data unit

doubleword A 64-bit data unit

x In some contexts, such as signal encodings, x (without italics) indicates a “don’t

care” condition.

x With italics, used to express an undefined alphanumeric value (e.g., a variable in

an equation); or a variable alphabetic character in a bit, register, or module name

(e.g., DSPI_x could refer to DSPI_A or DSPI_B).

n Used to express an undefined numerical value; or a variable numeric character in

a bit, register, or module name (e.g., EIFn could refer to EIF1 or EIF0).

1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data

transmission units. To simplify the discussion these units are referred to as words regardless of length.

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