VHDL语言实例教程：从基础到高级

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"该资源是一份VHDL语言例程集锦，主要针对初学者，由Ian Elliot（来自诺桑比亚大学）编写。这个文件包含了各种类型的硬件设计示例，展示了VHDL语言的多样性和强大功能。示例涵盖了从基本逻辑门描述的简单组合逻辑到复杂的系统，如微处理器的行为模型和相关内存。所有例子都可以用任何符合IEEE标准的VHDL模拟器进行仿真，许多还能用当前的综合工具进行综合。资源提供了层次结构链接，方便用户浏览不同类型的例程，包括组合逻辑、计数器、移位寄存器、存储器、状态机、寄存器、系统、模数转换器（ADC）和数模转换器（DAC）以及算术运算等。" 在VHDL语言例程集中，我们首先看到的是组合逻辑部分，其中包括了数据流风格、行为风格和结构风格的异或门实现，这些不同的实现方式展示了VHDL的灵活性。此外，还有其他逻辑门的示例，如三输入多数表决器、幅度比较器、四输入与非门（74x00系列）、二进制编码十进制到七段显示译码器以及双二选四解码器等，这些都是数字电路设计的基础。接下来是计数器和移位寄存器，这些是数字系统中常见的时序逻辑元素。计数器用于计数和定时，移位寄存器则用于数据的串行输入和并行输出。通过这些例程，学习者可以理解如何用VHDL描述这些器件的工作原理和功能。存储器部分包含了VHDL对于RAM和ROM等存储设备的描述，这对于理解和设计存储系统至关重要。状态机则演示了如何用VHDL描述有限状态自动机，这是控制逻辑设计的关键。寄存器部分展示了如何用VHDL定义和操作简单的数据寄存器，这在数据处理和传输中起到关键作用。系统部分可能包含更复杂的硬件模型，例如微处理器的行为模型，这有助于理解和设计微处理器系统。最后，ADC和DAC的例程解释了如何用VHDL实现模拟信号和数字信号之间的转换，这是数字信号处理和通信系统中的重要组成部分。算术运算部分则涵盖了基本的数学运算，如加减乘除，这对于设计计算单元非常有用。总而言之，这个VHDL语言例程集锦是一个全面的学习资源，它覆盖了数字系统设计的各个方面，对于想要掌握VHDL语言的初学者来说，是一份极其宝贵的资料。通过这些实例，学习者不仅能深入理解VHDL语法，还能了解到实际硬件设计的思路和方法。

Examples of VHDL Descriptions

tin(i) <= '1';

end generate;

t1_size : if i > 0 generate

tin(i) <= q(i-1) and tin(i-1);

end generate;

end v1;

Counter using Multiple Wait Statements

This example shows an inefficient way of describing a counter.

--vhdl model of a 3-state counter illustrating the use

--of the WAIT statement to suspend a process.At each wait

--statement the simulation time is updated one cycle,transferring

--the driver value to the output count.

--This architecture shows that there is no difference between

--WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'

ENTITY cntr3 IS

PORT(clock : IN BIT; count : OUT NATURAL);

END cntr3;

ARCHITECTURE using_wait OF cntr3 IS

BEGIN

PROCESS

BEGIN

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 2;

END PROCESS;

END using_wait;

Counter using a Conversion Function

This counter uses a natural number to hold the count value and converts it into a bit_vector for output. Illustrates the use of a function.

--4-bit binary up counter with asynchronous reset 2/2/93

ENTITY cntr4bit IS

PORT(reset,clock : IN BIT; count : OUT BIT_VECTOR(0 TO 3));

END cntr4bit;

ARCHITECTURE dataflow OF cntr4bit IS

--interface function to generate output bit_vector from

--internal count value.

FUNCTION nat_to_bv(input : NATURAL; highbit : POSITIVE)

RETURN BIT_VECTOR IS

VARIABLE temp : NATURAL := 0;

VARIABLE output : BIT_VECTOR(0 TO highbit);

BEGIN

temp := input;

--check that input fits into (highbit+1) bits

ASSERT (temp <= (2**(highbit + 1) - 1))

REPORT "input no. is out of range" SEVERITY ERROR;

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Examples of VHDL Descriptions

--generate bit values

FOR i IN highbit DOWNTO 0 LOOP

IF temp >= (2**i)

THEN output(i) := '1';

temp := temp - (2**i);

ELSE output(i) := '0';

END IF;

END LOOP;

RETURN output;

END nat_to_bv;

--signal to hold current count value

SIGNAL intcount : NATURAL := 0;

BEGIN

--conditional natural signal assignment models counter

intcount <= 0 WHEN (reset = '1') ELSE

((intcount + 1) MOD 16) WHEN (clock'EVENT AND clock = '1')

ELSE intcount;

--interface function converts natural count to bit_vector count

count <= nat_to_bv(intcount,3);

END;

Quad 2-input Nand

Simple concurrent model of a TTL quad nand gate.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT00 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT00;

architecture VER1 of HCT00 is

begin

Y1 <= A1 nand B1 after 10 ns;

Y2 <= A2 nand B2 after 10 ns;

Y3 <= A3 nand B3 after 10 ns;

Y4 <= A4 nand B4 after 10 ns;

end VER1;

Dual 2-to-4 Decoder

A set of conditional signal assignments model a dual 2-to-4 decoder

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT139 is

port(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;

Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic);

end HCT139;

architecture VER1 of HCT139 is

begin

Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';

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Examples of VHDL Descriptions

Y21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';

Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';

Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1';

end VER1;

Quad D-Type Flip-flop

This example shows how a conditional signal assignment statement could be used to describe sequential logic (it is more common to use a process). The keyword 'unaffected' is equivalent to the 'null' statement in the sequential part

of the language. The model would work exactly the same without the clause 'else unaffected' attached to the end of the statement.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT175 is

port(D : in std_logic_vector(3 downto 0);

Q : out std_logic_vector(3 downto 0);

CLRBAR, CLK : in std_logic);

end HCT175;

architecture VER1 of HCT175 is

begin

Q <= (others => '0') when (CLRBAR = '0')

else D when rising_edge(CLK)

else unaffected;

end VER1;

Octal Bus Transceiver

This example shows the use of the high impedance literal 'Z' provided by std_logic. The aggregate '(others => 'Z')' means all of the bits of B must be forced to 'Z'. Ports A and B must be resolved for this model to work correctly (hence std_logic rather than

std_ulogic).

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT245 is

port(A, B : inout std_logic_vector(7 downto 0);

DIR, GBAR : in std_logic);

end HCT245;

architecture VER1 of HCT245 is

begin

A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');

B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');

end VER1;

Quad 2-input OR

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT32 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT32;

architecture VER1 of HCT32 is

begin

Y1 <= A1 or B1 after 10 ns;

Y2 <= A2 or B2 after 10 ns;

Y3 <= A3 or B3 after 10 ns;

Y4 <= A4 or B4 after 10 ns;

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