Virtex 6 FPGA时钟资源配置详览

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Virtex 6 FPGA 用户手册（UG362 v2.5，发布日期：2014年1月24日）是一份详尽的文档，专为Virtex 6系列FPGA设计者提供时钟资源配置指南。该手册详细介绍了如何有效地管理和配置这些高级FPGA的时钟系统，这对于保证设计的性能、稳定性和整体系统集成至关重要。 Virtex-6 FPGA是Xilinx公司的一款高性能逻辑器件，它集成了先进的布线技术和多路时钟管理功能。时钟资源是FPGA设计的核心组成部分，因为它们负责协调芯片内部各个逻辑模块的工作，确保数据在正确的时间同步下传输，避免潜在的竞态条件和数据错误。本手册涵盖了以下关键知识点： 1. **时钟网络设计**：Virtex 6 FPGA的时钟网络结构、时钟树设计、时钟缓冲器和驱动器的使用方法，以及如何选择合适的时钟源和时钟负载容限。 2. **时钟管理策略**：如何优化时钟频率，以平衡性能与功耗，以及如何处理多个时钟域间的同步问题。 3. **时钟抖动和噪声抑制**：介绍如何通过合理的布局布线和使用时钟缓冲器来降低时钟信号的质量问题，确保信号的可靠性。 4. **时钟锁定和恢复**：针对复位期间和系统启动过程中的时钟行为，手册提供了相应的技术细节和注意事项。 5. **电源时钟规划**：电源时钟（PLLs）的配置，包括时钟倍频、分频和相位调整，以及如何确保时钟稳定性和相位一致性。 6. **限制和注意事项**：Xilinx对使用手册内容的版权声明，以及开发者在使用过程中需要注意的法律义务、责任限制和可能的改动通知。 7. **错误处理和支持**：尽管Xilinx对文档的准确性不作保证，但它会根据情况更新文档以纠正错误，并可能提供技术支持，但不对技术支持产生的问题承担法律责任。这份手册对于任何从事Virtex 6 FPGA设计的工程师来说，都是不可或缺的参考资料，能够帮助他们充分利用器件的时钟资源，实现高效、稳定的设计。在实际应用中，设计师应遵循文档指导，并结合具体项目需求，灵活运用这些知识。

Clocking Resources www.xilinx.com 11

UG362 (v2.5) January 24, 2014

Global Clocking Resources

For more information on clock input pins, consult the Die Level Bank Numbering and Clock

Pins Overview section in UG365

: Virtex-6 FPGA Packaging and Pinout Specification.

Global Clocking Resources

Global clocks are a dedicated network of interconnect specifically designed to reach all

clock inputs to the various resources in an FPGA. These networks are designed to have low

skew and low duty cycle distortion, low power, and improved jitter tolerance. They are

also designed to support very high frequency signals.

Understanding the signal path for a global clock expands the understanding of the various

global clock resources. The global clocking resources and network consist of the following

paths and components:

• Global Clock Inputs

• Global Clock Buffers

• Clock Tree and Nets - GCLK

• Clock Regions

X-Ref Target - Figure 1-2

Figure 1-2: Inner I/O Column Single Region Clocking Structure

CMT

IOCL

Bank

40 I/Os

IOCR

Bank

40 I/Os

MMCM X0Yn

In Same Region

MMCM X0Yn

In Same Region

To B ank

Above

SRCC Pin Pair

MRCC Pin Pair

SRCC Pin Pair

Two Single

Region BUFIOs

Two Multi-

Region

BUFIOs

Two B U F R s

MRCC Pin Pair

HROWHROW

To Outer

Columns

Clocking

Region

40 CLBs

High

To Outer

Columns

MRCC Pin Pair

SRCC Pin Pair

To B ank

Above

To B ank

Below

SRCC = Single Region Clock Capable I/O

MRCC = Multi Region Clock Capable I/O

Single ended clocks must be connected

to the P-side of the differential pair.

To B ank

Below

UG362_c1_02_011609

12 www.xilinx.com Clocking Resources

UG362 (v2.5) January 24, 2014

Chapter 1: Clocking Resources

Global Clock Inputs

Virtex-6 FPGAs contain specialized global clock input locations for use as regular user

I/Os if not used as clock inputs. There are eight global clock inputs per device. Clock

inputs can be configured for any I/O standard, including differential I/O standards. Each

clock input can be either single-ended or differential. All eight clock inputs can be

differential if desired. When used as outputs, global clock input pins can be configured for

any output standard. Each global clock input pin supports any single-ended output

standard or any output differential standard. The global clock inputs are distributed across

four banks in the inner I/O columns for the most flexible selection of I/O standards.

Global Clock Input Buffer Primitives

The primitives in Table 1-1 are different configurations of the input clock I/O input buffer.

These two primitives work in conjunction with the Virtex-6 FPGA SelectIO™ resource by

setting the IOSTANDARD attribute to the desired standard. Refer to Chapter 1 of the

Virtex-6 FPGA SelectIO Resources User Guide for a complete list of possible I/O standards.

Clock Gating for Power Savings

The Virtex-6 FPGA clock architecture provides a straightforward means of implementing

clock gating for the purposes of powering down portions of a design. Most designs contain

several unused BUFGCE resources. A clock can drive a BUFGCE input, and a BUFGCE

output can drive distinct regions of logic. For example, if all the logic that is required to

always be operating is constrained to a few clocking regions, then the BUFGCE output can

drive those regions. Toggling the enable of the BUFGCE provides a simple means of

stopping all dynamic power consumption in the logic regions available for power savings.

The Xilinx Power Estimator (XPE) or the Xilinx Power Analyzer (XPower) tools are used to

estimate power savings. The difference is calculated by setting the frequency on the

corresponding clock net to 0 MHz or providing the appropriate stimulus data to the tool.

Global Clock Buffers

There are 32 global clock buffers in every Virtex-6 device. A global clock input can directly

connect from the P-side of the differential input pin pair to any global clock buffer input.

There are eight global clock pin inputs. The top/bottom half rules from previous Virtex

architectures no longer apply. Each differential global clock pin pair can connect to either a

differential or single-ended clock on the PCB. If using a single-ended clock, then the P-side

of the pin pair must be used because a direct connection only exists on this pin. For pin

naming conventions please refer to the Virtex-6 FPGA Packaging and Pinout Specification. If

a single-ended clock is connected to the P-side of a differential pin pair, then the N-side can

not be used as another single-ended clock pin. However, it can be used as a user I/O.

MMCMs in the top half of the device can only drive the BUFGs in the top half of the device

and MMCMs in bottom half can only drive BUFGs in the bottom half. Similarly, only

BUFGs in the same half of the device can be used as feedback to the MMCMs in the same

half of the device.

Table 1-1: Clock Buffer Primitives

Primitive Input Output Description

IBUFG I O Input clock buffer for single-ended I/O

IBUFGDS I, IB O Input clock buffer for differential I/O

Clocking Resources www.xilinx.com 13

UG362 (v2.5) January 24, 2014

Global Clocking Resources

Global clock buffers allow various clock/signal sources to access the global clock trees and

nets. The possible sources for input to the global clock buffers include:

• Global clock inputs

• Clock-capable inputs in the same half of the devices from the inner I/O columns

• Clock Management Tile (CMT) consisting of mixed-mode clock managers (two

MMCMs per CMT) driving BUFGs in the same half of the device

• Other global clock buffer outputs (BUFGs)

• General interconnect

• Regional clock buffers (BUFRs)

• Gigabit transceivers

The Virtex-6 FPGA clock-capable inputs can drive global clock buffers indirectly through

the vertical clock network that exists in the MMCM column. The 32 BUFGs are organized

into two groups of 16 BUFGs in the top and bottom of the device. Any resources (e.g., GTX

transceivers) connecting to the BUFGs directly have a top/bottom limitation. For example,

each MMCM in the top can only drive the 16 BUFGs residing in that top of the device.

Similarly, the MMCMs in the bottom drive the 16 BUFGs in the bottom.

All global clock buffers can drive all clock regions in Virtex-6 devices. However, only 12

different clocks can be driven in a single clock region. A clock region (40 CLBs) is a branch

of the clock tree consisting of 20 CLB rows up and 20 CLB rows down. A clock region only

spans halfway across the device.

The clock buffers are designed to be configured as a synchronous or asynchronous glitch-

free 2:1 multiplexer with two clock inputs. Virtex-6 device control pins provide a wide

range of functionality and robust input switching. In the Virtex-6 clocking architecture,

BUFGCNTRL multiplexers and all derivatives can be cascaded to adjacent clock buffers

within the group of 16 in the upper/lower half of the device, effectively creating a ring of

16 BUFGMUXes (BUFGCNTRL multiplexers) in the upper half and another ring of 16 in

the lower half. Figure 1-3 shows a simplified diagram of cascading BUFGs.

The following subsections detail the various configurations, primitives, and use models of

the Virtex-6 FPGA clock buffers.

X-Ref Target - Figure 1-3

Figure 1-3: Cascading BUFGs

ug362_c1_03_111510

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