24LC64芯片详细手册：低功耗I2C接口与特性概览

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24LC64芯片手册是一份详尽的技术文档，由Microchip Technology Inc.发布，专门针对24AA64/24LC64型号的电可擦除只读存储器(Electrically Erasable PROM)。这款64Kb的存储芯片具有以下关键特性： 1. **电源兼容性**：24LC64可以在低至1.8伏的单电源下工作，确保了设备在节能模式下的灵活性。它采用低功耗CMOS技术，典型工作电流低至1毫安，而在待机模式（I-temp条件下）的最大电流仅为1微安。 2. **内存组织**：芯片以8个8K字节（64Kb）块的形式进行组织，便于编程和数据访问。每个块内有1Kx8位的存储单元。 3. **接口设计**：24LC64采用了2线串行接口（I2C兼容），支持多设备级联，最多可达八个设备，这简化了系统布线并提高了通信效率。 4. **抗干扰特性**：输入引脚采用施密特触发器，有助于抑制噪声，同时输出斜率控制功能能有效减少地线反射，提高信号传输的可靠性。 5. **写操作特性**：支持自定时的写周期，包括自动擦除功能，且配备页写缓冲区，最大可写入32字节，写入速度较快，典型时间为2毫秒。 6. **保护机制**：硬件级别的写保护功能可以防止整个内存被意外修改，而作为串行ROM使用时，提供了额外的安全性。 7. **编程选项**：支持工厂快速编程（QTP），并且具有高抗静电（ESD）保护，能承受超过4000伏的电压冲击，确保长期稳定性能。 8. **耐久性和寿命**：该芯片可以执行高达1百万次的擦写和读取操作，数据保留时间长达200年，显示出其长久的使用寿命。 9. **封装形式**：24LC64提供多种封装选项，包括8针双列直插式（PDIP）、小外形引脚阵列（SOIC）、薄小型扁平封装（TSSOP）和多小外形封装（MSOP），满足不同应用场合的需求。 10. **温度范围**：芯片适用于广泛的环境条件，支持不同应用对温度的要求。总结来说，24LC64是一款功能强大的低功耗、串行接口、高度可编程的EEPROM，适合于需要长期数据存储、紧凑型设计和高效通信的电子设备中，如嵌入式系统、工业控制或物联网应用。通过阅读这份手册，用户能够深入理解芯片的工作原理、接口规范以及最佳实践，从而更有效地集成和使用这款存储芯片。

 2002 Microchip Technology Inc. DS21189F-page 5

24AA64/24LC64

2.0 FUNCTIONAL DESCRIPTION

The 24XX64 supports a bi-directional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus has to be controlled

by a master device which generates the serial clock

(SCL), controls the bus access and generates the

START and STOP conditions, while the 24XX64 works

as slave. Both master and slave can operate as trans-

mitter or receiver, but the master device determines

which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last six-

teen will be stored when doing a write operation. When

an overwrite does occur it will replace data in a first-in

first-out (FIFO) fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX64) will leave the data line

HIGH to enable the master to generate the STOP con-

dition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX64 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

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