Xilinx时序约束用户指南

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"《时序约束用户指南》是Xilinx公司发布的一份关于FPGA设计的重要文档，旨在帮助用户在开发与Xilinx硬件设备协同工作的设计时理解和应用时序约束。该用户指南提供了详细的时序约束知识，适用于版本v11.1.1，发布于2009年4月29日。文档内容涵盖了一系列规定和约定，包括排版和在线文档的样式指南。Xilinx强调，用户只能在开发与Xilinx硬件兼容的设计时使用此文档，并且未经许可，不得复制、分发或以任何形式传播文档内容。此外，Xilinx有权随时更改文档而无需提前通知，并且不承担因使用文档导致的任何责任。文档提供的信息‘按原样’提供，没有任何形式的保修，Xilinx也不保证提供技术支持或更新中的任何错误纠正。" 时序约束在FPGA设计中起着至关重要的作用，它定义了设计中逻辑门电路之间的信号传输时间限制，确保系统能够满足预定的性能指标，如工作频率和时钟周期。时序约束通常包括以下几类： 1. **时钟约束**：定义了设计中不同区域或模块的时钟路径，包括时钟源、时钟网络延迟以及时钟域间的同步要求。 2. **数据路径约束**：针对数据信号在逻辑门之间传递的路径，包括组合逻辑和触发器之间的延迟，确保数据在正确的时间到达目的地。 3. **建立和保持约束**：确保在时钟边沿到来之前，数据已经稳定在触发器的输入端，以及数据在时钟边沿之后保持稳定的时间。 4. **I/O约束**：定义输入/输出缓冲器的行为，包括输入数据的到达时间和输出数据的驱动时间，以适应外部设备的时序需求。 5. **部分重配置约束**：在支持部分重配置的FPGA中，用于指定哪些逻辑区域可以在运行时重新配置。 6. **电源和时钟管理约束**：控制电源域和时钟分区，优化功耗和性能。理解并正确设置这些约束对于成功实现FPGA设计至关重要，因为它们直接影响到综合工具如何布局和布线逻辑，以及最终实现的电路能否达到预期的时序性能。用户应根据具体的硬件平台和设计需求来定制时序约束，同时密切关注Xilinx提供的最新文档和指导，以确保设计的时效性和可靠性。

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Chapter 2: Timing Constraint Methodology

Basic Constraints Methodology

Timing requirements fall into into several global categories depending on the type of path

to be covered.

The most common types of path categories include:

• Input paths

• Synchronous element to synchronous element paths

• Path specific exceptions

• Output Paths

A Xilinx

timing constraint is associated with each of these global constraint types. The

most efficient way to specify these constraints is to begin with global constraints and add

path specific exceptions as needed. In many cases, only the global constraints are required.

The FPGA device implementation tools are driven by the specified timing requirements.

They assign device resources and expend the appropriate amount of effort necessary to

ensure the timing requirements are met. However, when a requirement is over-constrained

- or specified as a value greater than the design requirement - the effort spent by the tools

to meet this constraint increases significantly. This extra effort results in increased memory

use and tool runtime.

More importantly, over-constraint can result in loss of performance, not only for the

constraint in question, but for other constraints as well. For this reason, Xilinx recommends

that you specify the constraint values using the actual design requirements.

Xilinx recommends that you always comment the constraints file. This allows other

designers to understand why each constraint is used.

Include in your comments:

• Source of the constraint

• Whether the PERIOD constraint is based on an external clock

This Guide uses XCF constraint syntax examples. This format passes the design

requirements to the implementation tools. However, the easiest way to enter design

constraints is to use Constraints Editor.

Constraints Editor:

• Provides a unified location in which to manage all the timing constraints associated

with a design

• Provides assistance in creating timing constraints from the design requirements in

XCF syntax

Input Timing Constraints

This section discusses Input Timing Constraints and includes:

• “About Input Timing Constraints”

• “System Synchronous Inputs”

• “Source Synchronous Inputs”

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UG612 (v 11.1.1) April 29, 2009

Input Timing Constraints

About Input Timing Constraints

Input timing covers the data path from the external pin of the FPGA device to the internal

OFFSET IN constraint. The best way to specify the input timing requirements depends on

the type (source/system synchronous) and single data rate (SDR) or double data rate

(DDR) of the interface.

The OFFSET IN constraint defines the relationship between the data and the clock edge

used to capture that data at the pins of the FPGA device. When analyzing the OFFSET IN

constraint, the timing analysis tools automatically take all internal factors affecting the

delay of the clock and data into account. These factors include:

• Frequency and phase transformations of the clock

• Clock uncertainties

• Data delay adjustments

In addition to the automatic adjustments, you may also add additional input clock

uncertainty to the PERIOD constraint associated with the interface clock.

For more information on adding INPUT_JITTER, see “PERIOD Constraints” in Chapter 3,

“Timing Constraint Principles.”

The OFFSET IN constraint is associated with a single input clock. By default, the OFFSET

IN constraint covers all paths from the input pads of the FPGA device to the internal

synchronous elements that capture that data and are triggered by the specified OFFSET IN

clock. This application of the OFFSET IN constraint is called the global method. It is the

most efficient way to specify input timing.

System Synchronous Inputs

In a system synchronous interface, a common system clock both transfers and captures the

data. This interface uses a common system clock. The board trace delays and clock skew

limit the operating frequency of the interface. The lower frequency also results in the

system synchronous input interface typically being an SDR application.

In the system synchronous SDR application example, shown in Figure 2-1, “Simplified

System Synchronous interface with associated SDR timing,” the data is transmitted from

the source device on one rising clock edge and captured in the FPGA device on the next

rising clock edge.

The global OFFSET IN constraint is the most efficient way to specify the input timing for a

system synchronous interface. In this method, one OFFSET IN constraint is defined for

each system synchronous input interface clock. This single constraint covers the paths of

Figure 2-1: Simplified System Synchronous interface with associated SDR timing

X11047

Source Device

REG

CLK

Data

System Clock

FPGA

REG

CLK

DataData

System Clock

Transmit

Edge

Capture

Edge

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Chapter 2: Timing Constraint Methodology

all input data bits that are captured in synchronous elements triggered by the specified

input clock.

To specify the input timing:

• Define the clock PERIOD constraint for the input clock associated with the interface

• Define the global OFFSET IN constraint for the interface

Example

A timing diagram for an ideal System Synchronous SDR interface is shown in Figure 2-2,

“Timing diagram for an ideal System Synchronous SDR interface.” The interface has a

clock period of 5 ns, The data for both bits of the bus remains valid for the entire period.

The global OFFSET IN constraint is:

OFFSET = IN value VALID value BEFORE clock;

In the OFFSET IN constraint, the OFFSET=IN <value> determines the time from the

capturing clock edge to the time in which data first becomes valid. In this system

synchronous example, the data becomes valid 5 ns prior to the capturing clock edge. In the

OFFSET IN constraint, the VALID <value> determines the duration in which data

remains valid. In this example, the data remains valid for 5 ns.

For this example, the complete OFFSET IN specification with associated PERIOD

constraint is:

NET "SysCLk" TNM_NET = "SysClk";

TIMESPEC "TS_SysClk" = PERIOD "SysClk" 5 ns HIGH 50%;

OFFSET = IN 5 ns VALID 5 ns BEFORE "SysClk";

This global constraint covers both the data bits of the bus:

• data1

• data2

Source Synchronous Inputs

In a source synchronous input interface, a clock is regenerated and transmitted along with

the data from the source device along similar board traces. This clock is then used to

capture the data in the FPGA device. The board trace delays and board skew no longer

limit the operating frequency of the interface. The higher frequency also results in the

source synchronous input interface typically being a dual data rate (DDR) application. In

Figure 2-2: Timing diagram for an ideal System Synchronous SDR interface

X11048

DataData 1

DataData 2

SysClk

Transmit

Edge

Capture

Edge

PERIOD = 5 ns

OFFSET IN BEFORE = 5ns

VALID = 5 ns

综合工具如何知道某个约束应用于哪些信号？

凡是以某个时钟操作的数据线都被优化。

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Chapter 2: Timing Constraint Methodology

The global OFFSET IN constraint for the DDR case is:

OFFSET = IN value VALID value BEFORE clock RISING;

OFFSET = IN value VALID value BEFORE clock FALLING;

In the OFFSET IN constraint, OFFSET=IN <value> determines the time from the

capturing clock edge in which data first becomes valid. In this source synchronous input

example, the rising data becomes valid 1.25 ns prior to the rising clock edge. The falling

data also becomes valid 1.25 ns prior to the falling clock edge. In the OFFSET IN constraint,

the VALID <value> determines the duration in which data remains valid. In this

example, both the rising and falling data remains valid for 2.5 ns.

For this example, the complete OFFSET IN specification with associated PERIOD

constraint is:

NET "SysCLk" TNM_NET = "SysClk";

TIMESPEC "TS_SysClk" = PERIOD "SysClk" 5 ns HIGH 50%;

OFFSET = IN 1.25 ns VALID 2.5 ns BEFORE "SysClk" RISING;

OFFSET = IN 1.25 ns VALID 2.5 ns BEFORE "SysClk" FALLING;

This global constraint covers both the data bits of the bus:

• data1

• data2

This section discusses Register-To-Register Timing Constraints and includes:

• “About Register-To-Register Timing Constraints”

• “Automatically Related Synchronous DCM/PLL Clock Domains”

• “Manually Related Synchronous Clock Domains”

• “Asynchronous Clock Domains”

About Register-To-Register Timing Constraints

synchronous data paths between internal registers. The PERIOD constraint:

• Defines the timing requirements of the clock domains

• Analyzes the paths within a single clock domain

• Analyzes all paths between related clock domains

• Takes into account all frequency, phase, and uncertainty differences between the clock

domains during analysis

For more information, see “PERIOD Constraints” in Chapter 3, “Timing Constraint

Principles.”

The application and methodology for constraining synchronous clock domains falls under

several common cases. These categories include:

• “Automatically Related Synchronous DCM/PLL Clock Domains”

• “Manually Related Synchronous Clock Domains”

• “Asynchronous Clock Domains”

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