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Board Design Page 7
MAX 10 FPGA Design GuidelinesDecember 2014 Altera Corporation
2.
Ensure board support the required features:
■ Data decompression—if you enable data compression, the storage requirement and
the programming time (writing to flash) are reduced. The configuration time (writing
to CRAM) is increased.
■ Design security—this feature utilizes a 128-bit security key to protect the designs
from unauthorized copying, reverse engineering, and tampering. The devices can
decrypt configuration bitstreams using the AES algorithm. Design security is not
available for the JTAG configuration scheme.
■ Dual configuration—this feature is supported only in self-download mode.
■ SEU mitigation—dedicated circuitry in the devices perform cyclic redundancy check
(CRC) error detection and check for SEU errors automatically. To detect SEU errors,
use the
CRC_ERROR
pin to flag errors and design your system to take appropriate
action. If you do not enable the CRC error detection feature, you can also use the
CRC_ERROR
pin as a design I/O pin.
For more information, refer to the MAX 10 FPGA Configuration User Guide.
3.
Plan for the Auto-restart after configuration error option
To reset the device internally by driving the
nSTATUS
pin low when a configuration error
occurs, enable the Auto-restart after configuration error option. The device releases its
nSTATUS
pin after the reset time-out period. This behavior allows you to re-initiate the
configuration cycle. The
nSTATUS
pin requires an external 10-kΩ pull-up resistor to
V
CCIO
.
4.
Estimating configuration file size
To estimate the configuration file size, convert your configuration file in uncompressed
Raw Binary File (.rbf). The .rbf file size provides the approximate uncompressed
configuration file sizes.
Use uncompressed .rbf size only to estimate the file size before design compilation.
Different configuration file formats, such as Hexadecimal (Intel-Format) File (.hex) or
Tabular Text File (.ttf) format, have different file sizes.
For more information on the uncompressed .rbf sizes for MAX 10 devices, refer to the
MAX 10 FPGA Configuration User Guide.
5.
Review available on-chip debugging tools
Take advantage of on-chip debugging features to analyze internal signals and perform
advanced debugging techniques.
Different debugging tools work better for different systems and different designers.
Early planning can reduce the time spent debugging, and eliminates design changes
later to accommodate your preferred debugging methodologies. Adding debug pins may
not be enough, because of internal signal and I/O pin accessibility on the device.
For more information about in-system debugging tools in the Quartus II software, refer
to the following documents:
■ System Debugging Tools Overview in the Quartus II Handbook
■ Virtual JTAG (sld_virtual_jtag) Megafunction User Guide
Table 4. Early Board Design Planning Checklist (Part 2 of 4)
No. v Checklist items