Xilinx时序约束用户指南

时序约束，xilinx

需积分: 16 34 浏览量更新于2024-08-02 收藏 1.01MB PDF 举报

身份认证购VIP最低享 7 折!

30元优惠券

"XilinxTimingConstraintsUserGuideUG612(v1.0.0)December9,2008" 在高性能应用中，时序约束是确保数字系统正确、高效运行的关键因素。Xilinx的时序约束用户指南是专门针对这一问题编写的，旨在帮助设计者在基于Xilinx硬件设备的设计中实现时序闭合。该文档详细阐述了如何有效地设置和管理时序约束，以满足高性能应用的需求。时序约束是指在设计过程中，对数字电路中的信号传播时间和关键路径的限制。这些约束定义了逻辑门或触发器之间数据必须在多长时间内传输，以及何时应采样这些数据，以确保系统的正确操作。在Xilinx FPGA（现场可编程门阵列）或ASIC（应用特定集成电路）设计中，正确的时序约束是达到预期性能目标和满足时钟周期要求的基础。 Xilinx Timing Constraints User Guide涵盖了以下几个核心主题： 1. **时序分析基础**：解释了时序分析的基本概念，包括时钟路径、组合逻辑路径和时钟树综合（CTS）。理解这些基本概念有助于确定设计中需要约束的关键路径。 2. **时钟约束**：详细介绍了如何定义时钟网络，包括时钟源、时钟分配和时钟域跨越（CDC）约束。时钟约束对于确保时钟同步和避免数据竞争至关重要。 3. **路径约束**：讨论了如何指定数据路径的延迟限制，这包括最大延迟（setup）和最小延迟（hold）约束。这些约束确保数据在正确的时间到达目的地。 4. **接口约束**：提供了关于如何为标准接口如PCIe、DDR内存和其他接口设置时序约束的指导。 5. **功耗约束**：介绍如何通过功耗优化时序约束来降低设计的静态和动态功耗。 6. **约束语法和工具**：详述了Xilinx的约束语言（如UCF, XDC）以及如何使用Vivado等设计工具进行约束设置。 7. **调试和验证**：指导用户如何检查和调试时序约束，以确保满足设计的性能要求。请注意，文档中明确指出，Xilinx不对文档内容承担任何责任，且保留随时更改而不事先通知的权利。用户应根据最新的文档版本进行设计，同时理解Xilinx不保证文档中可能存在的错误，并且不承担因使用文档而产生的任何技术支持或协助的责任。 Xilinx Timing Constraints User Guide是Xilinx设计者的重要参考资料，它提供了一套全面的方法来理解和处理时序约束，以确保设计在性能、功耗和可靠性方面达到最佳状态。

资源详情

资源推荐

14 www.xilinx.com Xlinx Timing Constraints User Guide

UG612 (v1.0.0) December 5, 2008

Chapter 2: Timing Constraint Methodology

the VALID <value> determines the duration in which data remains valid. In this

example, both the rising and falling data remains valid for 2.5 ns.

For this example, the complete OFFSET IN specification with associated PERIOD

constraint is:

NET "SysCLk" TNM_NET = "SysClk";

TIMESPEC "TS_SysClk" = PERIOD "SysClk" 5 ns HIGH 50%;

OFFSET = IN 1.25 ns VALID 2.5 ns BEFORE "SysClk" RISING;

OFFSET = IN 1.25 ns VALID 2.5 ns BEFORE "SysClk" FALLING;

This global constraint covers both the data bits of the bus:

• data1

• data2

This section discusses Register-To-Register Timing Constraints and includes:

• “About Input Timing Constraints”

• “Automatically Related Synchronous DCM/PLL Clock Domains”

• “Manually Related Synchronous Clock Domains”

• “Asynchronous Clock Domains”

About Register-To-Register Timing Constraints

synchronous data paths between internal registers. The PERIOD constraint:

• Defines the timing requirements of the clock domains

• Analyzes the paths within a single clock domain

• Analyzes all paths between related clock domains

• Takes into account all frequency, phase, and uncertainty differences between the clock

domains during analysis

For more information, see “PERIOD Constraints” in Chapter 3, “Timing Constraint

Principles.”

The application and methodology for constraining synchronous clock domains falls under

several common cases. These categories include:

• “Automatically Related Synchronous DCM/PLL Clock Domains”

• “Manually Related Synchronous Clock Domains”

• “Asynchronous Clock Domains”

By allowing the tools to automatically create clock relationships for DLL/DCM/PLL

output clocks, and manually defining relationships for externally related clocks, all

synchronous cross clock domain paths are covered by the appropriate constraints, and

properly analyzed. Using PERIOD constraints that follow this methodology eliminates the

need for additional cross-clock-domain constraints.

Xlinx Timing Constraints User Guide www.xilinx.com 15

UG612 (v1.0.0) December 5, 2008

Automatically Related Synchronous DCM/PLL Clock Domains

The most common type of clock circuit is one in which:

• The input clock is fed into a DLL/DCM/PLL

• The outputs are used to clock the synchronous paths in the device

In this case, the recommended methodology is to define a PERIOD constraint on the input

clock to the DLL/DCM/PLL.

By placing the PERIOD constraint on the input clock, the Xilinx tools automatically:

• Derive a new PERIOD constraint for each of the DLL/DCM/PLL output clocks

• Determine the clock relationships between the output clock domains, and

automatically perform an analysis for any paths between these clock domains.

Example

The circuit of an input clock driving a DCM is shown inFigure 2-5, “The input clock of the

design goes to a DCM example.”

The PERIOD constraint syntax for this example is:

NET "ClockName" TNM_NET = "TNM_NET_Name";

TIMESPEC "TS_name" = PERIOD "TNM_NET_Name" PeriodValue HIGH HighValue%;

In the PERIOD constraint, the PeriodValue defines the duration of the clock period. In

this case, the input clock to the DCM has a period of 5 ns. The HighValue of the PERIOD

constraint defines the percent of the clock waveform that is HIGH. In this example, the

waveform has a 50/50 duty cycle resulting in a HighValue of 50%.

The syntax for this example is:

NET "ClkIn" TNM_NET = "ClkIn";

TIMESPEC "TS_ClkIn" = PERIOD "ClkIn" 5 ns HIGH 50%;

Based on the input clock PERIOD constraint given above, the DCM automatically:

• Creates two output clock constraints for the DCM outputs

• Performs analysis between the two domains

Manually Related Synchronous Clock Domains

In some cases the relationship between synchronous clock domains can not be

automatically determined by the tools - for example, when related clocks enter the FPGA

device on separate pins. In this case, Xilinx recommends that you:

• Define a separate PERIOD constraint for each input clock

• Define a manual relationship between the clocks

Figure 2-5: The input clock of the design goes to a DCM example

REG

CLK

RE G

CLK

DC M

CLKIN

CLK1X

CLK2X

Related Path

CL K2X

CL K1X

Trans mi t Edge

Capture Edge

PERIOD = 5 ns

16 www.xilinx.com Xlinx Timing Constraints User Guide

UG612 (v1.0.0) December 5, 2008

Chapter 2: Timing Constraint Methodology

Once you define the manual relationship, all paths between the two synchronous domains

are automatically analyzed. The analysis takes into account all frequency, phase, and

uncertainty information.

The Xilinx constraints system allows you to define complex manual relationships between

clock domains using the PERIOD constraint including clock frequency and phase

transformations.

To define complex manual relationships between clock domains using the PERIOD

constraint:

• Define the PERIOD constraint for the primary clock

• Define the PERIOD constraint for the related clock using the first PERIOD constraint

as a reference

For more information on using the PERIOD constraint to define clock relationships, see

“PERIOD Constraints” in Chapter 3, “Timing Constraint Principles.”

Two related clocks enter the FPGA device through separate external pins, as shown in

Figure 2-6, “Two related clocks entering the FPGA device through separate external pins.”

• The first clock (CLK1X) is the primary clock

• The second clock (CLK2X180) is the related clock

The PERIOD constraint syntax for this example is:

NET "PrimaryClock" TNM_NET = "TNM_Primary";

NET "RelatedClock" TNM_NET = "TNM_Related";

TIMESPEC "TS_primary" = PERIOD "TNM_Primary" PeriodValue HIGH

HighValue%;

TIMESPEC "TS_related" = PERIOD "TNM_Related" TS_Primary_relation PHASE

value;

In the related PERIOD definition, the PERIOD value is defined as a time unit (period)

relationship to the primary clock. The relationship is expressed in terms of the primary

clock TIMESPEC. In this example CLK2X180 operates at twice the frequency of CLK1X

which results in a PERIOD relationship of one-half.

In the related PERIOD definition, the PHASE value defines the difference in time between

the rising clock edge of the source clock and the related clock. In this example, since the

CLK2X180 clock is 180 degrees shifted, the rising edge begins 1.25 ns after the rising edge

of the primary clock.

Figure 2-6: Two related clocks entering the FPGA device through separate external

pins

REG

CLK

REG

CLK

CLK1X

Related Path

CLK2X180

CLK1X

Tr an smit Ed ge

Ca ptu re Ed ge

PE RIOD = 5 ns

CLK2X180

Xlinx Timing Constraints User Guide www.xilinx.com 17

UG612 (v1.0.0) December 5, 2008

The syntax for this example is:

NET "Clk1X" TNM_NET = "Clk1X";

NET "Clk2X180" TNM_NET = "Clk2X180";

TIMESPEC "TS_Clk1X" = PERIOD "Clk1X" 5 ns;

TIMESPEC "TS_Clk2X180" = PERIOD "Clk2X180" TS_Clk1X/2 PHASE + 1.25 ns ;

Asynchronous Clock Domains

Asynchronous clock domains are those in which the source and destination clocks do not

have a frequency or phase relationship. Since the clocks are not related, it is not possible to

determine the final relationship for setup and hold time analysis. For this reason, Xilinx

recommends that you use proper asynchronous design techniques to ensure the successful

capture of data. One example of proper asynchronous design technique is to use a FIFO

design element to capture and transfer data between asynchronous clock domains. While

not required, in some cases you may wish to constrain the maximum data path delay in

isolation without regard to clock path frequency or phase relationship.

The Xilinx constraints system allows you to constrain the maximum data path delay

without regard to source and destination clock frequency and phase relationship. This

requirement is specified using the FROM-TO constraint with the DATAPATHONLY

keyword.

To constrain of the maximum data path delay without regard to source and destination

clock frequency and phase relationship:

• Define a time group for the source synchronous elements

• Define a time group for the destination synchronous elements

• Define the maximum delay of the data paths using the FROM-TO constraint between

the two time groups with DATAPATHONLY keyword.

For more information on using the FROM-TO constraint with the DATAPATHONLY

keyword, see “FROM:TO (Multi-Cycle) Constraints” in Chapter 3, “Timing Constraint

Principles.”

Example

Two unrelated clocks enter the FPGA device through separate external pins as shown in

Figure 2-7, “Two unrelated clocks entering the FPGA device through separate external

pins.”

• The first clock (CLKA) is the source clock

• The second clock (CLKB) is the destination clock

Figure 2-7: Two unrelated clocks entering the FPGA device through separate

external pins

REG

CL K

REG

CL K

CLKA

Data_A_B

CLKB

剩余93页未读，继续阅读

picassoye

粉丝: 2
资源: 5

Xilinx时序约束用户指南

Synopsys_Timing_Constraints_and_Optimization_User_Guide.pdf

Timing Constraints and Clock Tree Synthesis

synopsys timing constraints and optimization user guide

timing constraints

timing constraints wizard

quartus中怎么查看时序约束文件

vivado设置建立保持时间的方法

FPGA 输入输出时序约束

STA Basic Tutorial

VCCO vivado 设置

ise A时钟26mhz b时钟300mhz 设置false

紫光fpga怎么约束相位

EDA 工具是怎么报timing的？

verilog hdl

vivado时序约束实例工程

FPGA时序约束课程

uvm monitor

start technology mapping

xdc ddr4 vcu118 zcu104

register_fail:AMBA:AXI3:signal_valid_rdata_when_rvalid_high_check] Description: Monitor Check for X or Z on RDATA when RVALID is high

最新资源