UDA1341TS：经济型音频CODEC用于MD家用和便携应用

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"UDA1341TS是一款经济型音频CODEC，适用于MiniDisc（MD）家用音响和便携式应用。该芯片提供多种格式数据接口，内置数字声音处理功能，先进的音频配置选项，并具备模拟前端、可编程增益放大器、模数转换器、数字自动增益控制、过载检测、静音功能等特性。" uda1341ts是Philips Semiconductors推出的一款集成音频编解码器，专为MiniDisc家庭音响系统和便携式设备设计。这款芯片具有以下主要特点： 1. **通用性**：UDA1341TS设计用于适应各种音频应用场景，如MD播放器，既适合家用也适合便携式设备。 2. **多格式数据接口**：它支持多种音频数据格式，能够灵活地与不同的数字音频源进行通信，确保兼容性。 3. **数字声音处理**：内置的数字信号处理功能包括了数字自动增益控制(AGC)，可以自动调整输入信号的增益，保持输出稳定。 4. **高级音频配置**：用户可以根据需求调整芯片的参数，实现定制化的音频体验。 5. **模拟前端**：芯片包含了模拟前端部分，用于处理来自外部麦克风或线路输入的模拟信号。 6. **可编程增益放大器(PGA)**：PGA允许精确控制输入信号的增益，以适应不同音源的灵敏度。 7. **模数转换器(ADC)**：高质量的ADC将模拟信号转换为数字信号，用于进一步处理。 8. **数字自动增益控制(AGC)**：AGC有助于防止输入信号过大导致的失真，确保输出音频的质量。 9. **AGC状态检测**：芯片能检测并报告AGC的工作状态，帮助系统监控和优化性能。 10. **数字混频器**：数字混频器可以混合多个音频信号，创建复杂的声音效果。 11. **减采样滤波器(ADC)**：在ADC部分，减采样滤波器用于降低采样率，减少处理负担。 12. **过载检测(ADC)**：防止输入信号过强导致的损坏，保护内部电路。 13. **静音功能(ADC/Mute)**：可快速静音输入或输出信号，便于控制播放。 14. **插值滤波器(DAC)**：在数字到模拟转换过程中，插值滤波器用于提高输出音频的分辨率。 15. **峰值检测器**：监测音频信号的峰值，防止输出过载。 16. **快速静音(Quickmute)**：快速响应的静音机制，确保音频切换的平滑。 17. **噪声整形器(DAC)**：通过噪声整形技术，提升数字音频的信噪比。 18. **滤波流数字到模拟转换器(FSDAC)**：这种特殊的DAC技术提供了更高质量的音频输出。 19. **L3接口**：L3接口允许芯片与其他系统组件进行高速数据交换，确保音频数据的实时传输。 UDA1341TS以其丰富的功能和灵活性，为MiniDisc设备提供了高性价比的音频解决方案，涵盖了从模拟信号采集到数字信号处理再到高质量模拟信号输出的全过程。

2002 May 16 7

Philips Semiconductors Product speciﬁcation

Economy audio CODEC for MiniDisc (MD)

home stereo and portable applications

UDA1341TS

7 FUNCTIONAL DESCRIPTION

7.1 System clock

The UDA1341TS accommodates slave mode only, this

means that in all applications the system devices must

provide the system clock. The system frequency is

selectable. The options are 256f

, 384f

or 512f

The system clock must be locked in frequency to the digital

interface signals.

7.2 Pin compatibility

The UDA1341TS is partially pin compatible with the

UDA1340M and UDA1344TS, making an upgrade of a

printed-circuit board from UDA1340M to UDA1341TS

easier. The pins that are compatible with the UDA1340M

are marked in Fig.3.

7.3 Analog front end

The analog front end of the UDA1341TS consists of two

stereo ADCs with a Programmable Gain Amplifier (PGA)

in channel 2. The PGA is intended to pre-amplify a

microphone signal applied to the input channel 2.

Input channel 1 has a selectable 0 or 6 dB gain stage, to

be controlled via the L3-interface. In this way, input signals

of 1 V (RMS value) or 2 V (RMS value) e.g. from a

CD source can be supported using an external resistor of

12 kΩ in series with the input channel 1. The application

modes are given in Table 1.

Table 1 Application modes using input gain stage

Note

1. If there is no need for 2 V (RMS value) input signal

support, the external resistor should not be used.

7.4 Programmable Gain Ampliﬁer (PGA)

The PGA can be set via the L3-interface at the gain

settings: −3, 0, 3, 9, 15, 21 or 27 dB.

7.5 Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1341TS consists of two

3rd-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched

capacitor implementation. The over-sampling ratio is 128.

7.6 Digital Automatic Gain Control (AGC)

Input channel 2 has a digital AGC to compress the

dynamic range when a microphone signal is applied to

input channel 2. The digital AGC can be switched on and

off via the L3-interface. In the on state the AGC

compresses the dynamic range of the input signal of input

channel 2. Via the L3-interface the user can set the

parameters of the AGC: attack time, decay time and output

level. When the AGC is set off via the L3-interface, the gain

of input channel 2 can be set manually. In this case the

gain of the PGA and digital AGC are combined. The range

of the gain of the input channel 2 is from −3 to +60.5 dB in

steps of 0.5 dB.

7.7 AGC status detection

The AGCSTAT signal from the digital AGC is HIGH when

the gain level of the AGC is below 8 dB. This signal can be

used to give the PGA a new gain setting via the

L3-interface and to power e.g. a LED.

7.8 Digital mixer

The two stereo ADCs (including the AGC) can be used in

four modes:

• ADC1 only mode (for line input); input channel 2 is off

• ADC2 only mode, including PGA and digital AGC (for

microphone input); input channel 1 is off

• ADC1 + ADC2 mixer mode, including PGA and AGC

• ADC1 and ADC2 double differential mode (improved

ADC performance).

Important: In order to prevent crosstalk between the line

inputs no signal should be applied to the microphone input

in the double differential mode.

In all modes (except the double differential mode) a

reference voltage is always present at the input of the

ADC. However, in the double differential mode there is no

reference voltage present at the microphone input.

In the mixer mode, the output signals of both ADCs in

channel 1 and channel 2 (after the digital AGC) can be

mixed with coefficients that can be set via the L3-interface.

The range of the mixer coefficients is from 0 to −∞ dB in

1.5 dB steps.

RESISTOR

(12 kΩ)

INPUT

GAIN

SWITCH

MAXIMUM INPUT VOLTAGE

Present 0 dB 2 V (RMS value) input signal;

note 1

Present 6 dB 1 V (RMS value) input signal

Absent 0 dB 1 V (RMS value) input signal

Absent 6 dB 0.5 V (RMS value) input signal

2002 May 16 8

Philips Semiconductors Product speciﬁcation

Economy audio CODEC for MiniDisc (MD)

home stereo and portable applications

UDA1341TS

7.9 Decimation ﬁlter (ADC)

The decimation from 128f

is performed in two stages.

The first stage realizes 3rd order characteristic,

decimating by 16. The second stage consists of

3 half-band filters, each decimating by a factor of 2.

Table 2 Decimation ﬁlter characteristics

7.10 Overload detection (ADC)

This name is convenient but a little inaccurate. In practice

the output is used to indicate whenever that output data, in

either the left or right channel, is bigger than −1 dB (actual

figure is −1.16 dB) of the maximum possible digital swing.

If this condition is detected the OVERFL output is forced

HIGH for at least 512f

cycles (11.6 ms at f

= 44.1 kHz).

This time-out is reset for each infringement.

7.11 Mute (ADC)

On recovery from power-down or switching on of the

system clock, the serial data output on pin DATAO is held

at LOW level until valid data is available from the

decimation filter. This time depends on whether the

DC-cancellation filter is selected:

• DC cancel off:

; t = 23.2 ms at f

= 44.1 kHz

• DC cancel on:

; t = 279 ms at f

= 44.1 kHz.

7.12 Interpolation ﬁlter (DAC)

The digital filter interpolates from 1f

to 128f

by means of

a cascade of a recursive filter and a Finite Impulse

Response (FIR) filter.

Table 3 Interpolation ﬁlter characteristics

7.13 Peak detector

In the playback path a peak level detector is build in.

The position of the peak detection can be set via the

L3-interface to either before or after the sound features.

The peak level detector is implemented as a peak-hold

detector, which means that the highest sound level is hold

until the peak level is read out via the L3-interface. After

read-out the peak level registers are reset.

7.14 Quick mute

A hard mute can be activated via the static pin QMUTE.

When QMUTE is set HIGH, the output signal is instantly

muted to zero. Setting QMUTE to LOW, the mute is

instantly de-activated.

7.15 Noise shaper (DAC)

The 3rd-order noise shaper operates at 128f

. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique allows for high

signal-to-noise ratios. The noise shaper output is

converted into an analog signal using a filter stream

digital-to-analog converter.

ITEM CONDITIONS

VALUE

(dB)

Passband ripple 0 to 0.45f

±0.05

Stop band >0.55f

−60

Dynamic range 0 to 0.45f

108

Overall gain input channel 1;

0 dB input

−1.16

sin x

------------

1024

-------------

12288

----------------

ITEM CONDITIONS

VALUE

(dB)

Passband ripple 0 to 0.45f

±0.03

Stop band >0.55f

−50

Dynamic range 0 to 0.45f

108

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