Msp430f149单片机技术规格与应用

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"msp430f149数据手册" MSP430F149是一款由德州仪器（TI）推出的微控制器，是MSP430系列的一部分，特别适用于低功耗应用。该数据手册是官方提供的详细技术文档，为初学者提供了全面了解这款单片机芯片特性的指南。 MSP430F149的主要特点包括： 1. **低工作电压范围**：芯片可以在1.8V至3.6V的宽电压范围内正常工作，这使得它适用于各种电源限制的场合。 2. **超低功耗**：在不同的工作模式下，MSP430F149表现出极低的能耗。在1MHz频率下，活动模式（Active Mode）的电流消耗仅为280μA，待机模式（Standby Mode）下电流消耗仅为1.6μA，而关闭模式（Off Mode，RAM保持）时则低至0.1μA。 3. **五种节能模式**：芯片提供五种不同的电源管理模式，以适应不同应用的需求，确保在不使用时能最大程度地降低功耗。 4. **快速唤醒**：从待机模式唤醒至工作状态只需不到6μs的时间，确保了高效的应用响应。 5. **16位RISC架构**：采用16位精简指令集计算（RISC）架构，执行周期仅为125ns，提高了处理速度和效率。 6. **12位ADC**：集成的12位模数转换器具有内部参考电压、采样保持功能和自动扫描特性，适用于多种信号采集应用。 7. **定时器**：包括16位Timer_B，带有7个捕捉/比较和阴影寄存器，以及16位Timer_A，带有3个捕捉/比较寄存器，为定时和脉冲控制提供强大支持。 8. **片上比较器**：内置比较器，可进行电压比较等操作。 9. **串行编程**：支持串行板载编程，无需外部编程电压，简化了开发和维护流程。 10. **程序安全**：提供可编程代码保护功能，通过安全熔丝确保代码安全。 11. **串行通信接口**：具备USART（通用同步/异步收发传输器）功能，可作为异步UART或同步SPI接口。MSP430F149系列有两款变体，MSP430x14x包含两个USART（USART0和USART1），而MSP430x13x仅有一个USART0。此外，MSP430F149系列有不同的存储配置，如MSP430F133拥有8KB+256B的闪存和256B的RAM，MSP430F135则提供16KB+256B的闪存和512B的RAM，这些差异满足了不同复杂度应用的需求。 MSP430F149是一款高性能、低功耗的微控制器，适用于需要高效能和节能的嵌入式系统设计，例如物联网设备、便携式电子设备、传感器节点和自动化控制系统等。通过深入学习其数据手册，开发者能够充分利用这款芯片的特性，实现高效、可靠的设计。

General-Purpose Register

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-Purpose Register

R10

R11

General-Purpose Register

R14

R15

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SLAS272F − JULY 2000 − REVISED JUNE 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in conjunc-

tion with seven addressing modes for source

operand and four addressing modes for destina-

tion operand.

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator respectively. The remain-

ing registers are general-purpose registers.

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

instruction set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; the address modes are listed

in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5

Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC

Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) −−> M(TONI)

Absolute F F MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)

Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)

Indirect

autoincrement

F MOV @Rn+,Rm MOV @R10+,R11

M(R10) −−> R11

R10 + 2−−> R10

Immediate F MOV #X,TONI MOV #45,TONI #45 −−> M(TONI)

NOTE: S = source D = destination

  

  

SLAS272F − JULY 2000 − REVISED JUNE 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up

External Reset

Watchdog

Flash memory

WDTIFG

KEYV

(see Note 1)

Reset 0FFFEh 15, highest

NMI

Oscillator Fault

Flash memory access violation

NMIIFG (see Notes 1 & 4)

OFIFG (see Notes 1 & 4)

ACCVIFG (see Notes 1 & 4)

(Non)maskable

0FFFCh 14

Timer_B7 (see Note 5) TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13

Timer_B7 (see Note 5)

TBCCR1 to 6 CCIFGs,

TBIFG (see Notes 1 & 2)

Maskable 0FFF8h 12

Comparator_A CAIFG Maskable 0FFF6h 11

Watchdog timer WDTIFG Maskable 0FFF4h 10

USART0 receive URXIFG0 Maskable 0FFF2h 9

USART0 transmit UTXIFG0 Maskable 0FFF0h 8

ADC12 (see Note 6) ADC12IFG (see Notes 1 & 2) Maskable 0FFEEh 7

Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6

Timer_A3

TACCR1 CCIFG,

TACCR2 CCIFG,

TAIFG (see Notes 1 & 2)

Maskable 0FFEAh 5

I/O port P1 (eight flags)

P1IFG.0 to P1IFG.7

(see Notes 1 & 2)

Maskable 0FFE8h 4

USART1 receive URXIFG1 Maskable 0FFE6h 3

USART1 transmit UTXIFG1 0FFE4h 2

I/O port P2 (eight flags)

P2IFG.0 to P2IFG.7

(see Notes 1 & 2)

Maskable 0FFE2h 1

0FFE0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

4. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable

it.

5. Timer_B7 in MSP430x14x(1) family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interrupt

flags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs.

6. ADC12 is not implemented on the 14x1 devices.

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