JEDEC Standard No. 308-U0-RCA
-i-
DDR5 UDIMM Raw Card Annex A
Contents
Page
1 Scope ................................................................................................................................................. 1
2 DDR5 Unbuffered DIMM Design File ............................................................................................. 1
3 Module Configuration ....................................................................................................................... 1
4 SDRAM Configuration ..................................................................................................................... 2
5 Supported Speeds .............................................................................................................................. 2
6 Design Deviations ............................................................................................................................. 2
7 General Layout .................................................................................................................................. 3
8 Functional Block Diagram ................................................................................................................ 4
9 Sideband Bus Routing ....................................................................................................................... 6
10 Clock Net Structure ........................................................................................................................... 7
11 Data Net Structure – DQ, DQS_t, DQS_c ........................................................................................ 8
12 Address and Command Net Structure Routing ................................................................................. 9
13 Control Net Structure Routing ........................................................................................................ 10
14 DIMM Impedance Profile ............................................................................................................... 11
15 ALERT_n Net Structure Routing .................................................................................................... 12
16 RESET_n Net Structure Routing .................................................................................................... 13
17 Cross Section Recommendations .................................................................................................... 14
Tables
Table 1 — DDR5 UDIMM Design File ........................................................................................................ 1
Table 2 — Module Configuration ................................................................................................................. 1
Table 3 — SDRAM Configuration ............................................................................................................... 2
Table 4 — Supported Speeds ........................................................................................................................ 2
Table 5 — Design Deviations ....................................................................................................................... 2
Table 6 — Trace Lengths for Host and Local Signals .................................................................................. 6
Table 7 — Trace Lengths for Clock to SDRAM Load Net Structures ......................................................... 7
Table 8 — Trace Lengths for DQ[31:00]_A, DQS[03:00]_t_A, DQS[03:00]_c_A Trace Lengths for
DQ[31:00]_B, DQS[03:00]_t_B, DQS[03:00]_c_B ................................................................... 8
Table 9 — Trace Lengths for Address and Command Net Structures .......................................................... 9
Table 10 — Trace Lengths for Control Net Structures ............................................................................... 10