Microchip LAN8740: 单芯片以太网PHY，支持节能802.3az与多种功能

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lan8740数据手册提供了高性能的单芯片以太网物理层收发器（PHY）解决方案，专为满足各种应用需求而设计。这款产品由Microchip Technology Inc. 在2013年至2015年间发布，DS00001987A是其核心文档。该芯片的主要亮点包括： 1. **能源效率**：符合IEEE 802.3az标准，支持节能以太网，有助于降低功耗，满足现代电子设备对低能耗的需求。 2. **诊断功能**：提供电缆诊断支持，便于用户监控和维护网络连接的健康状况。 3. **唤醒ON LAN (WoL)**：支持通过局域网唤醒待机设备，广泛应用于网络设备的自动化控制。 4. **灵活电源管理**：采用全面的flexPWR技术，具备灵活的电源管理架构，可适应不同电压范围，如LVCMOS，工作电压范围为+1.8V到+3.3V，同时内置1.2V降压稳压器，支持关断功能。 5. **自动MDIX**：内置高性能HP Auto-MDIX支持，自动检测并适配直通（T）和交叉（C）线缆模式，简化了网络安装。 6. **紧凑封装**：32针VQFN封装，RoHS合规，仅为5x5x0.9毫米的极小尺寸，适合空间有限的应用环境。 7. **确定性性能**：在MIIMode下，内部100Mb/s环回延迟保持较低，确保数据传输的稳定性。 lan8740适用于众多领域，如： - **家庭娱乐**：如机顶盒、网络打印机、服务器等。 - **测试与测量**：用于仪器仪表和测试设备。 - **主板集成**：在主板上实现内置网络功能。 - **嵌入式通信**：电信设备、视频录制/播放系统。 - **宽带设备**：Cable Modems/Routers、DSL Modems/Routers及数字视频录像机。 - **IP和视频电话**：支持语音和视频通信。 - **无线接入点**：Wi-Fi AP应用。 - **数字电视**：电视接收和媒体播放设备。 - **数字媒体服务器**：如流媒体服务和多媒体适配器。 - **游戏机**：游戏设备可能需要高速网络连接。 - **PoE应用**：支持PoE（Power over Ethernet），即通过以太网线供电，适用于安全摄像头和其他需要远程供电的设备。使用lan8740能带来高性能、低功耗、易部署以及高度集成的优势，是构建高效、稳定以太网解决方案的理想选择。对于开发人员来说，这是一款值得关注的芯片，可以显著简化产品设计，提高系统的整体效能。

LAN8740A/LAN8740Ai

DS00001987A-page 16  2013-2015 Microchip Technology Inc.

2.2 Buffer Types

TABLE 2-9: BUFFER TYPES

Buffer Type Description

IS Schmitt-triggered input

O12 Output with 12 mA sink and 12 mA source

VIS Variable voltage Schmitt-triggered input

VO8 Variable voltage output with 8 mA sink and 8 mA source

VOD8 Variable voltage open-drain output with 8 mA sink

PU 50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups

are always enabled.

Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on

internal resistors to drive signals external to the device. When connected to a load

that must be pulled high, an external resistor must be added.

PD 50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-

downs are always enabled.

Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely

on internal resistors to drive signals external to the device. When connected to a

load that must be pulled low, an external resistor must be added.

AI Analog input

AIO Analog bi-directional

ICLK Crystal oscillator input pin

OCLK Crystal oscillator output pin

P Power pin

Note: The digital signals are not 5 V tolerant. Refer to Section 5.1, "Absolute Maximum Ratings*" for additional

buffer information.

Note: Sink and source capabilities are dependent on the VDDIO voltage. Refer to Section 5.1, "Absolute Maxi-

mum Ratings*" for additional information.

 2013-2015 Microchip Technology Inc. DS00001987A-page 17

LAN8740A/LAN8740Ai

3.0 FUNCTIONAL DESCRIPTION

This chapter provides functional descriptions of the various device features. These features have been categorized into

the following sections:

• Transceiver

• Auto-Negotiation

• HP Auto-MDIX Support

• MAC Interface

• Serial Management Interface (SMI)

• Interrupt Management

• Configuration Straps

• Miscellaneous Functions

• Application Diagrams

3.1 Transceiver

3.1.1 100BASE-TX TRANSMIT

The 100BASE-TX transmit data path is shown in Figure 3-1. Each major block is explained in the following subsections.

3.1.1.1 100BASE-TX Transmit Data Across the MII/RMII Interface

For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The data

is latched by the transceiver’s MII block on the rising edge of TXCLK. The data is in the form of 4-bit wide 25 MHz data.

For RMII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate valid data. The

data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The data is in the form of 2-bit wide 50

MHz data.

3.1.1.2 4B/5B Encoding

The transmit data passes from the MII/RMII block to the 4B/5B encoder. This block encodes the data from 4-bit nibbles

to 5-bit symbols (known as “code-groups”) according to Table 3-1. Each 4-bit data-nibble is mapped to 16 of the 32 pos-

sible code-groups. The remaining 16 code-groups are either used for control information or are not valid.

The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The

remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is

/I/, a transmit error code-group is /H/, etc.

FIGURE 3-1: 100BASE-TX TRANSMIT DATA PATH

MAC

Driver

MLT-3

Converter

NRZI

Converter

4B/5B

Encoder

CAT-5RJ45

25 MHz by

5 bits

NRZI

MLT-3MLT-3

MLT-3

Scrambler

and PISO

MII/RMII

25 MHz

by 4 bits

Ext Ref_CLK (for RMII only)

PLL

MII 25 MHz by 4 bits

RMII 50 MHz by 2 bits

MLT-3

Magnetics

125 Mbps Serial

TX_CLK

(for MII only)

 2013-2015 Microchip Technology Inc. DS00001987A-page 19

LAN8740A/LAN8740Ai

3.1.1.3 Scrambling

Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band

peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire

channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being

radiated by the physical wiring.

The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in multiple-transceiver

applications, such as repeaters or switches, each transceiver will have its own scrambler sequence.

The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.

3.1.1.4 NRZI and MLT-3 Encoding

The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125 MHz NRZI

data stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a

code bit “1” and the logic output remaining at the same level represents a code bit “0”.

3.1.1.5 100M Transmit Driver

The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on outputs TXP and

TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-T and 100BASE-TX signals pass

through the same transformer so that common “magnetics” can be used for both. The transmitter drives into the 100 Ω

impedance of the CAT-5 cable. Cable termination and impedance matching require external components.

3.1.1.6 100M Phase Lock Loop (PLL)

The 100M PLL locks onto reference clock and generates the 125 MHz clock used to drive the 125 MHz logic and the

100BASE-TX transmitter.

3.1.2 100BASE-TX RECEIVE

The 100BASE-TX receive data path is shown in Figure 3-2. Each major block is explained in the following subsections.

FIGURE 3-2: 100BASE-TX RECEIVE DATA PATH

MAC

A/D

Converter

MLT-3

Converter

NRZI

Converter

4B/5B

Decoder

Magnetics CAT-5RJ45

PLL

MII 25 MHz by 4 bits

RMII 50 MHz by 2 bits

RX_CLK

(for MII only)

25 MHz by

5 bits

NRZI

MLT-3MLT-3 MLT-3

6 bit Data

Descrambler

and SIPO

125 Mbps Serial

DSP: Timing

recovery, Equalizer

and BLW Correction

MLT-3

MII/RMII

25 MHz

by 4 bits

Ext Ref_CLK (for RMII only)

LAN8740A/LAN8740Ai

DS00001987A-page 20  2013-2015 Microchip Technology Inc.

3.1.2.1 100M Receive Input

The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC

samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer, it generates

6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels

such that the full dynamic range of the ADC can be used.

3.1.2.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and ampli-

tude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer

can restore the signal for any good-quality CAT-5 cable between 1 m and 100 m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the iso-

lation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)

on the received signal will result. To prevent corruption of the received data, the transceiver corrects for BLW and can

receive the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125 MHz clock. A multiplexer, controlled by the timing unit of the DSP,

selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to

extract the serial data from the received signal.

3.1.2.3 NRZI and MLT-3 Decoding

The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an

NRZI data stream.

3.1.2.4 Descrambling

The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel

Out (SIPO) conversion of the data.

During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once

synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.

Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols

within a window of 4000 bytes (40 µs). This window ensures that a maximum packet size of 1514 bytes, allowed by the

IEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period,

receive operation is aborted and the descrambler re-starts the synchronization process.

3.1.2.5 Alignment

The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)

pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of

frame.

3.1.2.6 5B/4B Decoding

The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is pre-

sented on the RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC pre-

amble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid data is

available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End of

Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assert

the carrier sense and receive data valid signals.

Note: These symbols are not translated into data.

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