SDIO简化规范：版本3.00详解

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"SD Specifications Part E1 SDIO Simplified Specification Version 3.00是2011年2月25日发布的SD卡协会技术委员会的文档，是SD、SDIO、SDHC开发者的重要参考资料。该文档包含了SDIO简化规范的第3.00版，详细介绍了SDIO接口的技术规格和功能更新。" 本文档主要涵盖了以下几个关键知识点： 1. **SDIO（Secure Digital Input/Output）**：SDIO是一种扩展SD卡功能的接口标准，不仅支持存储，还允许其他设备如Wi-Fi模块、GPS接收器等通过SD卡接口与主机通信。 2. **版本3.00的更新**： - **定义了Embedded SDIO**：这使得SDIO卡可以直接集成到设备内部，增强了其在嵌入式系统中的应用可能性。 - **Ultra High Speed Bus Speed Mode (UHS-I)**：引入了超高速总线速度模式，提高了数据传输速率，最大可达104MB/s，满足了高清视频和其他高带宽应用的需求。 - **Power Control Extension (Power State Control)**：电源控制扩展功能，提供了更精细的电源管理，以适应不同设备的能耗需求，同时提高能效。 - **Asynchronous Interrupt in 4-bit mode**：在4位模式下支持异步中断，使得设备可以无需持续占用总线就能发送中断信号，提高了系统响应效率。 - **Shared Bus for supporting multiple devices**：共享总线设计，允许多个SDIO设备共用同一总线，减少了硬件资源的占用，简化了系统设计。 3. **历史版本变更**： - 从1.10版到2.00版的更新包括：增加了改变总线速度的方法（正常速度最高25MHz，高速模式最高50MHz）、扩展操作电压范围至2.7-3.6V、合并物理属性和机械扩展部分并加入miniSDIO、添加嵌入式SDIO ATA标准功能接口代码以及修正了一些排版错误。 4. **SD3.0与SDHC 3.0 spec**：这些标签表明文档涵盖了SD 3.0标准和SDHC（High Capacity）3.0规格，意味着支持更高的存储容量和更快的数据传输速率。 5. **技术委员会**：SD Card Association的技术委员会负责制定和维护这些规格，确保SD、SDIO和SDHC设备的互操作性和兼容性。 SD Specifications Part E1 SDIO Simplified Specification Version 3.00是理解SDIO接口和相关设备开发的关键资源，它不仅提供了技术规格，还详细描述了如何利用这些规范来提升设备性能和用户体验。对于任何涉及SDIO技术的软件开发者、硬件工程师或系统设计师来说，这个文档都是不可或缺的参考。

SDIO Simplified Specification Version 3.00

2. SDIO Signaling Definition

2.1 SDIO Card Types

This specification defines two types of SDIO cards. The Full-Speed card supports SPI, 1-bit SD and the 4-bit

SD transfer modes at the full clock range of 0-25MHz. Full-Speed SDIO cards have a data transfer rate of

over 100 Mb/second (10 MB/Sec). The second version of the SDIO card is the Low-Speed SDIO card. This

card requires only the SPI and 1-bit SD transfer modes. 4-bit support is optional. In addition, Low-Speed

SDIO cards shall support a full clock range of 0-400 KHz. The intended use of Low-Speed cards is to support

low-speed I/O capabilities with a minimum of hardware. The Low-Speed cards support such functions as

modems, bar-code scanners, GPS receivers etc. If a card is a 'Combo card' (memory plus SDIO) then

Full-Speed and 4-bit operation is mandatory for both the memory and SDIO portions of the card.

2.2 SDIO Card Modes

There are three bus modes defined for SD memory cards that also apply to SDIO Cards:

2.2.1 SPI (Card mandatory support)

The SPI bus topology is defined in Section 3.5.2 and the protocol is defined in Sections 3.6.2 and Chapter 7

of the Physical Layer Specification Version 3.0x. In this mode pin 8, which is undefined for memory, is used

as the interrupt pin. All other pins and signaling protocols are identical to the Physical Layer Specification.

New functions defined after the SDIO Version 2.00 may not be supported in the SPI mode.

2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support)

This mode is identical to the 1 data bit (narrow) mode defined for SD Memory in Section 3.6.1 of the Physical

Layer Specification. In this mode, data is transferred on the DAT[0] pin only. In this mode pin 8, which is

undefined for memory, is used as the interrupt pin and pin 9, which is undefined for memory, is used as the

read wait pin. All other pins and signaling protocols are identical to the Physical Layer Specification.

2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for

Low-Speed)

This mode is identical to the 4 data bit mode (wide) defined for SD Memory in Section 3.6.1 of the Physical

Layer Specification. In this mode, data is transferred on all 4 data pins (DAT[3:0]). In this mode the interrupt

pin is not available for exclusive use as it is utilized as a data transfer line. Thus, if the interrupt function is

required, special timing is required to provide interrupts. Refer to Section 8.1.2 for details of this operation.

UHS-I bus speed mode has been added from SDIO Version 3.00 onward. The 4-bit SD mode provides the

highest data transfer possible, up to 104 MB/sec.

2.3 SDIO Host Modes

If a SDIO aware host supports the SD transfer mode, it is recommended that both the 1-bit and 4-bit modes

be supported. While an SDIO host that supports only the 4-bit transfer mode is possible, its performance with

a Low-Speed SDIO card may be reduced. This is because the only means to transfer data to and from a

Low-Speed card would be the single byte per command transfer (using the IO_RW_DIRECT command

(CMD52), refer to Section 5.1).

SDIO Simplified Specification Version 3.00

3.1.2 Initialization by I/O Aware Host

An SDIO aware host sends CMD5 prior to the CMD55/ACMD41 pair, and thus would receive a valid OCR in

the R4 response to CMD5 and continue to initialize the card. Figure 3-2 shows the operation of an SDIO

aware host operating in the SD modes and Figure 3-3 shows the same operation for a host that operates in

the SPI mode.

If the I/O portion of a card has received no CMD5, the I/O Section remains inactive and shall not respond to

any command except CMD5. A combo card stays in the memory-only mode. If no memory is included on the

card, the card would not respond to any memory command. If the I/O aware host sends a CMD5 to the card,

the card responds with R4. The host then reads that R4 value and knows the number of available I/O

functions and if any SD memory exists.

A host that supports UHS-I sets S18R to 1 in the argument of CMD5 to request a change of the signal voltage

to 1.8V. If the card supports UHS-I and the current signal voltage is 3.3V, S18A is set to 1 in the R4 response.

If the signal voltage is already 1.8V, the card sets S18A to 0 so that host maintains the current signal voltage.

UHS-I is supported in SD mode and S18A is always 0 in SPI mode.

After the host has initialized the I/O portion of the card, it then reads the Common Information Area (CIA) of

the card (Refer to Section 6.8). This is done by issuing a read command, starting with the byte at address

00h, of I/O function 0. The CIA contains the Card Common Control Registers (CCCR) and the Function

Basic Registers (FBR). Also included in the CIA are pointers to the card's common Card Information

Structure (CIS) and each individual function's CIS. The CIS structure is defined in Chapter 16. The CIS

includes information on power, function, manufacturer and other things the host needs to determine if the I/O

function(s) is appropriate to power-up. If the host determines that the card should be activated, a register in

the CCCR area enables the card and each individual function. At this time, all functions of the I/O card are

fully available. In addition, the host can control the power consumption and enable/disable interrupts on a

function-by-function basis. This access to I/O does not interfere with memory access to the card if present.

Figure 3-2 shows Card Initialization Flow in SD mode and Figure 3-3 shows Card Initialization Flow in SPI

mode. UHS-I is not supported in SPI mode. Initialization Flow for an embedded device can be simplified by

removing unnecessary checks.

When receiving CMD5 with arg=0, the SDIO card returns an R4 response but does not start initialization of

the I/O function. The Version 3.00 SDIO card should start initialization sequence by receiving CMD5 without

waiting for CMD5 with WV=0.

Combo Cards can accept CMD15 with RCA=0000, as described in the Physical Layer Specification, but

there is an exception for SD memory only cards. Memory only cards require a non-zero RCA before the host

may issue CMD15. Thus, CMD15 shall be issued after CMD3 in the Standby state. In the case of ACMD41,

it shall accept RCA=0000h.

Application Notes:

As shown in Figure 3-2 and Figure 3-3, an SDIO aware host should send CMD5 arg=0 as part of the

initialization sequence after either Power On or a CMD 52 with write to I/O Reset. CMD5 arg=0 is

required for using a removal card due to the following reasons:

(1) There was 3.1V-3.5V voltage range legacy card and then whether host power supply can provide

the voltage in this range should be checked.

(2) There may be the card which requires CMD5 with WV= 0 to initialize the card.

CMD5 arg=0 may not be necessary for embedded system if the device does not require it.

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