SystemVerilog下功能验证方法的革新：撰写测试台架的艺术

需积分: 14 41 浏览量更新于2024-07-16 收藏 1.77MB PDF 举报

《利用SystemVerilog编写测试台：面向功能验证的生产力革命》是一本由Janick Bergeron撰写的专业书籍，出自Synopsys公司。该书针对当前电子工程领域面临的挑战，特别是随着摩尔定律的发展，传统的基于直觉的验证方法（如视觉检查模拟结果和手工设计测试用例）已难以满足效率需求。它强调了在现代系统级验证中采用结构化和自动化测试台（testbenches）设计的重要性，使用SystemVerilog这样的高级硬件描述语言进行编写。书中详细探讨了如何通过SystemVerilog进行高效、系统化的测试台设计，以应对复杂度日益增长的集成电路设计。SystemVerilog是一种广泛应用于硬件验证的高级语言，它提供了丰富的功能，如行为模型、数据流编程和并发特性，有助于创建可复用、模块化和易于维护的测试环境。作者旨在帮助读者理解如何利用SystemVerilog的特性，如assertions、覆盖分析、仿真信号断言（assertional debugging）、以及接口描述语言（interface description language, IDL），来设计更精准和全面的测试策略。通过这本书，读者可以学习到以下关键知识点： 1. **SystemVerilog语言基础**：理解SystemVerilog的关键语法、数据类型、流程控制语句，以及其在设计测试台时的优势。 2. **模块化和复用**：学习如何将测试代码分解为独立且可重用的模块，提高工作效率。 3. **测试策略设计**：掌握如何制定有效的测试用例，包括覆盖率目标和测试案例生成算法。 4. **模拟与验证方法**：理解模拟仿真技术在验证中的应用，如何利用波形分析、取样和触发机制进行深入调试。 5. **错误检测与诊断**：学习如何使用assertions和断言技术来确保设计符合预期行为，并在出现问题时进行快速定位。 6. **仿真环境设置**：熟悉如何配置和管理模拟器，以及如何集成SystemVerilog测试台到整个验证流程中。 7. **工具支持**：了解Synopsys等工具如何与SystemVerilog结合，提供自动化的测试生成和分析能力。 8. **实践案例分析**：通过实例展示如何将理论知识应用于实际设计项目，提高验证效率和质量。《利用SystemVerilog编写测试台》不仅是一本技术指南，也是一本实用手册，它将引导读者步入现代功能验证的高效道路，适应不断发展的半导体行业需求。对于从事电子设计验证工作的工程师来说，理解和掌握这些内容是提升职业竞争力的关键。

What This Book Is About

Writing Testbenches using SystemVerilog xvii

These unfamiliar semantics become important in understanding

what makes a well-implemented and robust testbench and in pro-

viding the necessary control and monitor features.

I will also present techniques for applying stimulus and monitoring

the response of a design, by abstracting the physical-level transac-

tions into high-level procedures using bus-functional models. The

architecture of testbenches built around these bus-functional mod-

els is important to create a layer of abstraction relevant to the func-

tion being verified and to minimize development and maintenance

effort. I also show some strategies for making testbenches self-

checking.

Creating random testbenches involves more than calling the $ran-

dom system task. I will show how random stimulus generators,

built on top of bus-functional models, can be architected and

designed to be able to produce the desired stimulus patterns. Ran-

dom generators must be easily externally constrained to increase

the likelihood that a set of interesting patterns will be generated.

Transaction-level modeling is another important concept presented

in this book. It is used to parallelize the implementation and verifi-

cation of a design and to perform more efficient simulations. A

transaction-level model must adequately emulate the functionality

of a design while offering orders of magnitudes in simulation per-

formance over the RTL model. Striking the correct level of accu-

racy is key to achieving that performance improvement.

This book has one large omission: assertions and formal verifica-

tion. It is not that they are not important. SystemVerilog includes

constructs and semantics for writing assertions and coverage prop-

erties using temporal expressions. Formal verification is already an

effective methodology for verifying certain classes of designs. It is

simply a matter of drawing a line somewhere. There are already

books on assertions

or formal verification. This book focuses on

the bread-and-butter of verification for the foreseeable future:

dynamic functional verification using testbenches

1. Cohen, Venkataramanan and Kumari, "SystemVerilog Assertion Hand-

book", VhdlCohen Publishing, 2005

Preface

xviii Writing Testbenches using SystemVerilog

WHAT PRIOR KNOWLEDGE YOU SHOULD HAVE

This book focuses on the functional verification of hardware

designs using SystemVerilog. I expect the reader to have at least a

basic knowledge of VHDL, Verilog, OpenVera or e. Ideally, you

should have experience in writing models and be familiar with run-

ning a simulation using any of the available VHDL or Verilog sim-

ulators. There will be no detailed description of language syntax or

grammar. It may be a good idea to have a copy of a language-

focused textbook or the SystemVerilog Language Reference Manual

as a reference along with this book. I do not describe a synthesiz-

able subset, nor limit the implementation of the verification tech-

niques to using that subset. Verification is a complex task: The

power of the SystemVerilog language will be used to its fullest.

I also expect that you have a basic understanding of digital hard-

ware design. This book uses several hypothetical designs from var-

ious application domains (video, datacom, computing, etc.). How

these designs are actually specified, architected and then imple-

mented is beyond the scope of this book. The content focuses on the

specification, architecture, then implementation of the verification

of these same designs.

Once you are satisfied with the content of this book and wish to put

it in practice, I recommend you pick up a copy of the Verification

Methodology Manual for SystemVerilog

(VMM). It is a book I co-

authored and wrote as a series of very specific guidelines on how to

implement testbenches using SystemVerilog. It uses all of the pow-

erful concepts introduced here. It also includes a set of base classes

that implements generic functionality that every testbench needs.

Why re-invent the wheel? I will refer to the first edition of the

VMM at relevant points in this book where further techniques,

guidelines or support can be found.

READING PATHS

You should really read this book from cover to cover. However, if

you are pressed for time, here are a few suggested paths.

1. Janick Bergeron, Eduard Cerny, Alan Hunter and Andrew Nightingale,

"Verification Methodology Manual for SystemVerilog", Springer 2005,

ISBN 0-387-25538-9

Preface

xx Writing Testbenches using SystemVerilog

ilog, being a superset of Verilog, benefits from the same smooth ini-

tial learning curve. However—like VHDL—Verilog and

SystemVerilog provide similar concepts: sequential statements, par-

allel constructs, structural constructs and the illusion of parallelism.

These concepts must be learned. Because of its lax requirements,

Verilog lulls the user into a false sense of security. The user believes

that he or she knows the language because there are no syntax

errors or because the simulation results appear to be correct. Over

time, and as a design grows, race conditions and fragile code struc-

tures become apparent, forcing the user to learn these important

concepts. Languages have the same area under the learning curve.

VHDL’s is steeper but Verilog’s goes on for much longer. Some

sections in this book take the reader farther down the Verilog learn-

ing curve.

SystemVerilog continues in Verilog’s footstep. Does that mean that

VHDL is dead? Technically, all VHDL capabilities are directly

available in SystemVerilog. And with the many capabilities avail-

able in SystemVerilog not available in VHDL, there are no longer

any technical reasons to use VHDL

. However, that decision is

never a purely technical one. There will be VHDL legacy code for

years to come. And companies with large VHDL legacies will con-

tinue to use it, if only in a co-simulation capacity. There is also an

effort by the VHDL IEEE Working Group to add these missing

capabilities to VHDL, known as VHDL-200x. Whether or not you

wish—or can afford—to wait for a me too language is again a busi-

ness decision.

Hardware Verification Languages

Hardware verification languages (HVLs) are languages that were

specifically designed to implement testbenches efficiently and pro-

ductively. Commercial solutions include OpenVera from Synopsys

and e from Cadence. Open-source solutions include the SystemC

Verification Library (SCV) from Cadence and Jeda from Juniper

Networks. There are also a plethora of home-grown solutions based

on Perl, SystemC, C++ or TCL. SystemVerilog includes all of the

1. Before anyone paints me as a Verilog bigot, I wish to inform my readers

that I learned VHDL first and have always had a slight preference

toward VHDL over Verilog.

Code Examples

Writing Testbenches using SystemVerilog xxi

features of a hardware verification language. When using System-

Verilog, it is no longer necessary to use a separate language for ver-

ification.

Making use of the verification features of SystemVerilog involves

more than simply learning a new syntax. Although one can con-

tinue to use a Verilog-like directed methodology with SystemVer-

ilog, using it appropriately requires a shift in the way verification is

approached and testbenches are implemented. The directed verifi-

cation strategy used with Verilog is the schematic capture of verifi-

cation. Using SystemVerilog with a constraint-driven random

verification strategy is the synthesis of verification. When used

properly, it is an incredible productivity boost (see Figure 2-16 on

page 56).

Does SystemVerilog mean that OpenVera, e and the other propri-

etary verification and assertion languages are going to die? The

answer is a definite no. SystemVerilog was created by merging

donated features and technologies from proprietary languages. It

did not invent nor create anything new other than integrating these

features and technologies under a consistent syntax and semantics.

The objectives of SystemVerilog are to lower the adoption and

ownership cost of verification tools and to create a broader market-

place through industry-wide support.

SystemVerilog accomplishes these objectives by being an industry

standard. But the problem with industry standards is that they

remain static while the semiconductor technologies continue to

advance. SystemVerilog will more than meet the needs of 90 per-

cent of the users for years to come. But leading edge users, who

have adopted HVLs years ago and are already pushing their limits,

will not be satisfied by SystemVerilog for very long. Proprietary

tools and languages will continue to evolve with those leading edge

projects. Hopefully, their trail-blazing efforts will be folded back

into a future version of SystemVerilog, where their art can become

science.

CODE EXAMPLES

A common complaint I received about the first edition was the lack

of complete examples. You’ll notice that in this book, like the first

two, code samples are still provided only as excerpts. I fundamen-

剩余430页未读，继续阅读

rukiafeng

粉丝: 0
资源: 1

SystemVerilog下功能验证方法的革新：撰写测试台架的艺术

使用SystemVerilog构建测试平台

SystemVerilog测试平台编写实战指南

数字IC设计验证：Writing Testbenches第二版

Writing testbenches using SystemVerilog pdf

Writing Testbenches using SystemVerilog

Writing-Testbenches-using-SystemVerilog.pdf

Writing Testbenches using System Verilog _systemverilog_

Writing Testbenches using System Verilog

writing testbench using systemverilog

如何学习FPGA.pdf

最新资源