Intel® PC Hub EG20T 数据手册：关键信息与规格

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本文档是关于Intel® Platform Controller Hub (PCB) EG20T 的详细数据手册，发布于2012年7月。Intel PCB EG20T 是一种关键组件，可能用于各种系统架构中，它作为平台控制器的核心部分，负责管理系统的输入/输出（I/O）事务、存储控制以及与外部设备的连接。该产品编号为324211-009US。文档的主要内容涵盖了产品概述、功能特性、电气规格、封装和引脚图、工作条件、性能指标、时序参数、电源管理选项、以及安全和合规性信息。其中特别强调了对于"Mission-Critical Applications"（关键任务应用）的注意事项，这些应用如果使用Intel PCB EG20T，可能导致人身伤害或死亡。因此，如果用户在这些高风险领域使用该产品，必须明确理解并接受可能存在的风险，并承担法律责任，包括对Intel及其子公司、子合同方、附属公司以及相关董事、官员和员工的损害赔偿责任。在详细描述部分，您将找到有关EG20T如何通过其先进的集成电路技术提供高速数据传输能力、支持多种接口标准（如PCIe、USB、SATA等）、以及如何实现低功耗和热管理策略的信息。此外，还会有针对硬件安装、配置和故障排查的指导，以及关于软件兼容性和驱动程序的要求。为了确保系统的可靠性和安全性，数据手册中包含了重要的警告信息，强调未经Intel许可，用户不得以任何方式修改或复制这份文档中的知识产权内容。任何关于产品销售和使用的责任和保修都应遵守Intel的标准销售条款，而不包括但不限于对特定用途的适用性、商业适销性或侵犯专利、版权或其他知识产权的任何保证。这份Platform Controller Hub EG20T 数据手册为用户提供了一个全面的参考框架，以便在设计和实施系统时了解其性能、限制和最佳实践，特别是对于那些处理高度敏感数据和操作的应用场景。对于开发者和系统集成者来说，它是必不可少的技术参考资料。

Intel

Platform Controller Hub EG20T—Contents

Intel

Platform Controller Hub EG20T

Datasheet July 2012

16 Order Number: 324211-009US

14.5.2.28 Station Address 1 Register....................................................... 529

14.5.2.29 Station Address 2 Register....................................................... 529

14.5.2.30 Station Address 3 Register....................................................... 529

14.5.2.31 Station Address 4 Register....................................................... 530

14.5.2.32 Station Address 5 Register....................................................... 530

14.5.2.33 Station Address 6 Register....................................................... 530

14.5.2.34 System Time Low Maximum Set Enable Register ........................ 531

14.5.2.35 System Time Low Maximum Set Register................................... 531

14.5.2.36 SOFT RESET Register (SRST) ................................................... 532

14.6 Functional Description ...................................................................................... 532

14.6.1 Theory of Operation (Ethernet Interfaces)................................................532

14.6.1.1 Priority Message Support......................................................... 533

14.6.1.2 PTP Message Formats ............................................................. 534

14.6.1.3 Sync Message ........................................................................ 536

14.6.1.4 Follow_Up Message ................................................................ 536

14.6.1.5 Delay_Req Message................................................................ 536

14.6.1.6 Delay_Resp Message .............................................................. 537

14.6.1.7 IPv6 Compatibility .................................................................. 537

14.6.1.8 Traffic Analyzer Support .......................................................... 537

14.6.1.9 MII Clocking Methods.............................................................. 537

14.6.1.10 System Time Clock Rate Set by Addend Register ........................ 538

14.6.1.11 MII Message Detection ............................................................ 538

14.6.2 IEEE1588 Over CAN.............................................................................. 542

14.6.3 Theory of Operation (Auxiliary Snapshots) ............................................... 543

14.6.3.1 Master Mode Programming Considerations ................................. 543

14.6.3.2 Slave Mode Programming Considerations................................... 543

15.0 I

C Interface.......................................................................................................... 545

15.1 Overview ........................................................................................................ 545

15.2 Features ......................................................................................................... 545

15.3 Register Address Map ....................................................................................... 545

15.3.1 PCI Configuration Registers ................................................................... 545

15.3.2 Memory-Mapped I/O Registers (BAR: MEM_BASE) .................................... 546

15.4 Registers ........................................................................................................ 547

15.4.1 PCI Configuration Registers ................................................................... 547

15.4.1.1 VID— Vendor Identification Register ......................................... 547

15.4.1.2 DID— Device Identification Register.......................................... 547

15.4.1.3 PCICMD— PCI Command Register............................................. 547

15.4.1.4 PCISTS—PCI Status Register....................................................548

15.4.1.5 RID— Revision Identification Register........................................ 549

15.4.1.6 CC— Class Code Register ........................................................ 549

15.4.1.7 MLT— Master Latency Timer Register ........................................ 550

15.4.1.8 HEADTYP— Header Type Register ............................................. 550

15.4.1.9 MEM_BASE— MEM Base Address Register .................................. 550

15.4.1.10 SSVID— Subsystem Vendor ID Register .................................... 551

15.4.1.11 SSID— Subsystem ID Register ................................................. 551

15.4.1.12 CAP_PTR— Capabilities Pointer Register .................................... 551

15.4.1.13 INT_LN— Interrupt Line Register .............................................. 551

15.4.1.14 INT_PN— Interrupt Pin Register ............................................... 552

15.4.1.15 MSI_CAPID—MSI Capability ID Register .................................... 552

15.4.1.16 MSI_NPR—MSI Next Item Pointer Register.................................552

15.4.1.17 MSI_MCR—MSI Message Control Register .................................. 552

15.4.1.18 MSI_MAR—MSI Message Address Register ................................. 553

15.4.1.19 MSI_MD—MSI Message Data Register ....................................... 553

15.4.1.20 PM_CAPID—PCI Power Management Capability ID Register .......... 554

15.4.1.21 PM_NPR—PM Next Item Pointer Register ................................... 554

15.4.1.22 PM_CAP—Power Management Capabilities Register ..................... 554

15.4.1.23 PWR_CNTL_STS—Power Management Control/Status Register...... 555

15.4.2 Memory-Mapped I/O Registers (BAR: MEM_BASE) .................................... 555

Intel

Platform Controller Hub EG20T

July 2012 Datasheet

Order Number: 324211-009US 17

Contents—Intel

Platform Controller Hub EG20T

15.4.2.1 Slave Address Register (I2CSADR) ........................................... 555

15.4.2.2 I

C Control Register (I2CCTL).................................................. 556

15.4.2.3 I

C Status Register (I2CSR) .................................................... 558

15.4.2.4 I

C Data Register (I2CDR) ...................................................... 560

15.4.2.5 I

C Bus Monitor Register (I2CMON) .......................................... 560

15.4.2.6 I

C Bus Transfer Rate Setting Counter (I2CBC) .......................... 561

15.4.2.7 I

C Mode Register (I2CMOD) ................................................... 561

15.4.2.8 I

C Buffer Mode Slave Address Register (I2CBUFSLV) ................. 562

15.4.2.9 I

C Buffer Mode Subaddress Register (I2CBUFSUB) .................... 563

15.4.2.10 I

C Buffer Mode Format Register (I2CBUFFOR) .......................... 564

15.4.2.11 I

C Buffer Mode Control Register (I2CBUFCTL)........................... 565

15.4.2.12 I

C Buffer Mode Interrupt Mask Register (I2CBUFMSK) ............... 565

15.4.2.13 I

C Buffer Mode Status Register (I2CBUFSTA) ........................... 566

15.4.2.14 I

C Buffer Mode Level Register (I2CBUFLEV) ............................. 568

15.4.2.15 EEPROM Software Reset Mode Format Register (I2CESRFOR)....... 568

15.4.2.16 EEPROM Software Reset Mode Control Register (I2CESRCTL) ....... 569

15.4.2.17 EEPROM Software Reset Mode Interrupt Mask Register

(I2CESRMSK) ......................................................................... 570

15.4.2.18 EEPROM Software Reset Mode Status Register (I2CESRSTA)........ 571

15.4.2.19 I

C Timer Register (I2CTMR) ................................................... 571

15.4.2.20 I

C Input Noise Filter Setting Register (I2CNF)........................... 572

15.4.2.21 SOFT RESET Register (SRST)................................................... 573

15.5 Functional Description...................................................................................... 574

15.5.1 Sequence of Operation ......................................................................... 574

15.5.1.1 Flow of Initial Setting ............................................................. 575

15.5.1.2 Flow of Slave Reception .......................................................... 578

15.5.1.3 Flow of Slave Transmission ..................................................... 579

15.5.1.4 Flow of Master Transmission.................................................... 580

15.5.1.5 Flow of Master Reception ........................................................ 581

15.5.1.6 Flow of Compound Mode (Receiving by Master after Transmitting

from Master) .......................................................................... 582

15.5.1.7 Flow of Compound Mode (Transmitting from Master after Receiving

by Master) ............................................................................. 584

15.5.1.8 Flow for Arbitration Lost and NACK Received.............................. 586

15.5.1.9 Flow for When Buffer Mode Used.............................................. 587

15.5.1.10 Flow for When EEPROM Software Reset Mode Used..................... 589

15.5.1.11 Flow for Switching Modes ........................................................ 589

15.5.1.12 Returning from Arbitration Lost................................................ 590

15.5.2 Waveform in Each Mode........................................................................ 590

15.5.2.1 Waveform Transmitted by Master............................................. 590

15.5.2.2 Waveform Received by Master ................................................. 591

15.5.2.3 Waveform Transmitted by Slave .............................................. 591

15.5.2.4 Waveform Received by Slave................................................... 591

15.5.2.5 Waveform of Compound Format (Master Transmission + Master

Reception) ............................................................................. 591

15.5.2.6 Waveform of Compound Format (Master Reception + Master

Transmission) ........................................................................ 592

15.5.2.7 Waveform for When Buffer Mode Used 1 ................................... 592

15.5.2.8 Waveform for When Buffer Mode Used 2 ................................... 592

15.5.2.9 Waveform for When Buffer Mode Used 3 ................................... 592

15.5.2.10 Waveform for When Buffer Mode Used 4 ................................... 593

15.5.2.11 Waveform for When Buffer Mode Used 5 ................................... 593

15.5.2.12 Waveform for When Buffer Mode Used 6 ................................... 594

15.5.2.13 Waveform for When Buffer Mode Used 7 ................................... 594

15.5.2.14 Waveform for When Buffer Mode Used 8 ................................... 595

15.5.2.15 Waveform of Clock Synchronization.......................................... 595

15.5.3 Timing Diagrams of Setup and Clear in I2CCSR ........................................ 596

15.5.3.1 I2CSR Timing Diagram When Viewed From the Master

(Transmitting Side) ................................................................. 597

Intel

Platform Controller Hub EG20T—Contents

Intel

Platform Controller Hub EG20T

Datasheet July 2012

18 Order Number: 324211-009US

15.5.3.2 I2CSR Timing Diagram When Viewed From the Slave (Receiving

Side) ..................................................................................... 597

15.5.3.3 I2CSR Timing Diagram When Viewed From the Slave (Transmitting

Side) ..................................................................................... 597

15.5.3.4 I2CSR Timing Diagram When Viewed From Master 1/Master 2

(Transmitting Side) ................................................................. 598

15.5.4 Timing Diagrams When Transmitting START, Repeated START, and STOP

Conditions ........................................................................................... 598

15.5.4.1 Timing Diagram When Transmitting a START Condition ............... 598

15.5.4.2 Timing Diagram When Transmitting a STOP Condition ................. 599

15.5.4.3 Timing Diagram When Transmitting a Repeated START Condition.. 599

15.5.5 Input Noise Filter..................................................................................599

15.5.6 Restrictions ......................................................................................... 600

16.0 GPIO...................................................................................................................... 601

16.1 Overview ........................................................................................................ 601

16.2 Features ......................................................................................................... 601

16.3 Register Address Map ....................................................................................... 601

16.3.1 PCI Configuration Registers ................................................................... 601

16.3.2 Memory-Mapped I/O Registers (BAR: MEM_BASE) .................................... 602

16.4 Registers ........................................................................................................ 602

16.4.1 PCI Configuration Registers ................................................................... 602

16.4.1.1 VID — Vendor Identification Register ........................................ 602

16.4.1.2 DID — Device Identification Register......................................... 603

16.4.1.3 PCICMD — PCI Command Register............................................ 603

16.4.1.4 PCISTS — PCI Status Register - Alan ........................................ 604

16.4.1.5 RID — Revision Identification Register....................................... 604

16.4.1.6 CC — Class Code Register ....................................................... 605

16.4.1.7 MLT — Master Latency Timer Register ....................................... 605

16.4.1.8 HEADTYP — Header Type Register ............................................ 605

16.4.1.9 MEM_BASE — MEM Base Address Register ................................. 606

16.4.1.10 SSVID — Subsystem Vendor ID Register ................................... 606

16.4.1.11 SSID — Subsystem ID Register ................................................ 606

16.4.1.12 CAP_PTR — Capabilities Pointer Register ................................... 607

16.4.1.13 INT_LN — Interrupt Line Register ............................................. 607

16.4.1.14 INT_PN — Interrupt Pin Register .............................................. 607

16.4.1.15 MSI_CAPID — MSI Capability ID Register .................................. 607

16.4.1.16 MSI_NPR — MSI Next Item Pointer Register............................... 608

16.4.1.17 MSI_MCR — MSI Message Control Register ................................ 608

16.4.1.18 MSI_MAR — MSI Message Address Register ............................... 609

16.4.1.19 MSI_MD — MSI Message Data Register ..................................... 609

16.4.1.20 PM_CAPID — PCI Power Management Capability ID Register ........ 609

16.4.1.21 PM_NPR — PM Next Item Pointer Register.................................. 609

16.4.1.22 PM_CAP — Power Management Capabilities Register ................... 610

16.4.1.23 PWR_CNTL_STS — Power Management Control/Status Register.... 610

16.4.2 Memory-Mapped I/O Registers (BAR: MEM_BASE) .................................... 611

16.4.2.1 IEN — Interrupt Enable Register............................................... 611

16.4.2.2 ISTATUS — Interrupt Status Register ........................................ 611

16.4.2.3 IDISP — Interrupt Source Register ........................................... 612

16.4.2.4 ICLR — Interrupt Clear Register ............................................... 613

16.4.2.5 IMASK — Interrupt Mask Register............................................. 613

16.4.2.6 IMASKCLR — Interrupt Mask Clear Register ............................... 614

16.4.2.7 PO — Port Output Register....................................................... 614

16.4.2.8 PI — Port Input Register.......................................................... 615

16.4.2.9 PM — Port Mode Register......................................................... 616

16.4.2.10 IM0 — Interrupt Mode Register 0.............................................. 616

16.4.2.11 IM1 — Interrupt Mode Register 1.............................................. 617

16.4.2.12 SRST — SOFT RESET Register.................................................. 618

16.5 Functional Description ...................................................................................... 619

Intel

Platform Controller Hub EG20T

July 2012 Datasheet

Order Number: 324211-009US 19

Contents—Intel

Platform Controller Hub EG20T

16.5.1 I/O Setting.......................................................................................... 619

16.5.2 Interrupt Setting Procedure ................................................................... 619

16.5.3 Operation of Various Interrupts.............................................................. 620

16.5.3.1 Falling Edge Interrupt............................................................. 620

16.5.3.2 Rising Edge Interrupt ............................................................. 620

16.5.3.3 “L” Level Input Interrupt ......................................................... 621

16.5.3.4 “H” Level Input Interrupt ........................................................ 622

16.5.3.5 Interrupt at Both Edges (Rising Edge/Falling Edge)..................... 623

16.5.4 Wakeup .............................................................................................. 624

17.0 UART ..................................................................................................................... 625

17.1 Overview ....................................................................................................... 625

17.2 Features ........................................................................................................ 625

17.3 Register Address Map ...................................................................................... 626

17.3.1 PCI Configuration Registers ................................................................... 626

17.3.2 Memory-Mapped I/O Registers (BAR: MEM_BASE).................................... 627

17.4 Registers........................................................................................................ 627

17.4.1 PCI Configuration Registers ................................................................... 627

17.4.1.1 VID— Vendor Identification Register ......................................... 627

17.4.1.2 DID— Device Identification Register ......................................... 628

17.4.1.3 PCICMD— PCI Command Register ............................................ 628

17.4.1.4 PCISTS—PCI Status Register ................................................... 629

17.4.1.5 RID— Revision Identification Register ....................................... 630

17.4.1.6 CC— Class Code Register ........................................................ 630

17.4.1.7 MLT— Master Latency Timer Register........................................ 630

17.4.1.8 HEADTYP— Header Type Register............................................. 631

17.4.1.9 IO_BASE— IO Base Address Register........................................ 631

17.4.1.10 MEM_BASE— MEM Base Address Register.................................. 631

17.4.1.11 SSVID— Subsystem Vendor ID Register.................................... 632

17.4.1.12 SSID— Subsystem ID Register ................................................ 632

17.4.1.13 CAP_PTR— Capabilities Pointer Register .................................... 632

17.4.1.14 INT_LN— Interrupt Line Register.............................................. 632

17.4.1.15 INT_PN— Interrupt Pin Register ............................................... 633

17.4.1.16 MSI_CAPID—MSI Capability ID Register .................................... 633

17.4.1.17 MSI_NPR—MSI Next Item Pointer Register ................................ 633

17.4.1.18 MSI_MCR—MSI Message Control Register.................................. 633

17.4.1.19 MSI_MAR—MSI Message Address Register................................. 634

17.4.1.20 MSI_MD—MSI Message Data Register....................................... 634

17.4.1.21 PM_CAPID—PCI Power Management Capability ID Register.......... 635

17.4.1.22 PM_NPR—PM Next Item Pointer Register ................................... 635

17.4.1.23 PM_CAP—Power Management Capabilities Register..................... 635

17.4.1.24 PWR_CNTL_STS—Power Management Control/Status Register ..... 636

17.4.2 Memory-Mapped I/O Registers (BAR: MEM_BASE).................................... 637

17.4.2.1 Transmit Buffer Register (THR) ................................................ 637

17.4.2.2 Receive Buffer Register (RBR).................................................. 637

17.4.2.3 Line Control Register (LCR) ..................................................... 637

17.4.2.4 Line Status Register (LSR) ...................................................... 639

17.4.2.5 FIFO Control Register (FCR) .................................................... 641

17.4.2.6 FIFO Control Register (FCR) .................................................... 642

17.4.2.7 Modem Control Register (MCR) ................................................ 643

17.4.2.8 Modem Status Register (MSR) ................................................. 644

17.4.2.9 Interrupt Identification Register (IIR) ....................................... 645

17.4.2.10 Interrupt Enable Register (IER)................................................ 647

17.4.2.11 Divisor Latches (DLL, DLM) ..................................................... 648

17.4.2.12 Scratch Pad Register (SCR) ..................................................... 652

17.4.2.13 Baud Rate Reference Clock Select Register (BRCSR) ................... 652

17.4.2.14 SOFT RESET Register (SRST)................................................... 653

17.5 Functional Description...................................................................................... 654

17.5.1 Interface Specifications......................................................................... 654

Intel

Platform Controller Hub EG20T—Contents

Intel

Platform Controller Hub EG20T

Datasheet July 2012

20 Order Number: 324211-009US

17.5.1.1 Transmit Timing ..................................................................... 654

17.5.1.2 Receive Timing ...................................................................... 654

17.5.1.3 Modem Timing ....................................................................... 655

17.5.2 Programming ....................................................................................... 655

17.5.3 FIFO Interrupt Mode Operation............................................................... 655

17.5.4 FIFO Polling Mode Operation .................................................................. 656

17.5.5 Auto Hardware Flow Operation ...............................................................656

17.5.6 Example of Software Processing Performed When a Receive Data Error

Occurs ................................................................................................ 657

17.5.6.1 When a Framing Error, Parity Error, or Break Error Is Received..... 657

17.5.6.2 When an Overrun Error Occurs................................................. 658

18.0 SPI ........................................................................................................................661

18.1 Introduction .................................................................................................... 661

18.1.1 Overview............................................................................................. 661

18.1.2 Features.............................................................................................. 661

18.2 Register Address Map ....................................................................................... 661

18.2.1 PCI Configuration Registers ................................................................... 661

18.2.2 Memory-Mapped Registers (BAR: MEM_BASE).......................................... 662

18.3 Registers ........................................................................................................ 663

18.3.1 PCI Configuration Registers ................................................................... 663

18.3.1.1 DID— Device Identification Register.......................................... 663

18.3.1.2 PCICMD— PCI Command Register............................................. 663

18.3.1.3 PCISTS—PCI Status Register....................................................664

18.3.1.4 RID— Revision Identification Register........................................ 665

18.3.1.5 CC— Class Code Register ........................................................ 665

18.3.1.6 MLT— Master Latency Timer Register ........................................ 666

18.3.1.7 HEADTYP— Header Type Register ............................................. 666

18.3.1.8 MEM_BASE— MEM Base Address Register .................................. 666

18.3.1.9 SSVID— Subsystem Vendor ID Register .................................... 667

18.3.1.10 SSID— Subsystem ID Register ................................................. 667

18.3.1.11 CAP_PTR— Capabilities Pointer Register .................................... 667

18.3.1.12 INT_LN— Interrupt Line Register .............................................. 667

18.3.1.13 INT_PN— Interrupt Pin Register ............................................... 668

18.3.1.14 MSI_CAPID—MSI Capability ID Register .................................... 668

18.3.1.15 MSI_NPR—MSI Next Item Pointer Register.................................668

18.3.1.16 MSI_MCR—MSI Message Control Register .................................. 668

18.3.1.17 MSI_MAR—MSI Message Address Register ................................. 669

18.3.1.18 MSI_MD—MSI Message Data Register ....................................... 669

18.3.1.19 ID—PCI Power Management Capability ID Register ..................... 670

18.3.1.20 PM_NPR—PM Next Item Pointer Register ................................... 670

18.3.1.21 PM_CAP - Power Management Capabilities Register..................... 670

18.3.1.22 PWR_CNTL_STS—Power Management Control/Status Register...... 671

18.3.2 Memory-Mapped I/O Registers (BAR: MEM_BASE) .................................... 671

18.3.2.1 SPI Control Register (SPCR)..................................................... 671

18.3.2.2 SPI Baud Rate Register (SPBRR) .............................................. 674

18.3.2.3 SPI Status Register (SPSR)...................................................... 676

18.3.2.4 SPI Write Data Register (SPDWR) ............................................. 677

18.3.2.5 SPI Read Data Register (SPDRR) .............................................. 678

18.3.2.6 SSN Expand Control Register (SSNXCR) .................................... 678

18.3.2.7 SOFT RESET Register (SRST) ................................................... 680

18.4 Functional Description ...................................................................................... 680

18.4.1 Master Mode and Slave Mode ................................................................. 680

18.4.2 Control of the Polarity and Phase of the Serial Clock.................................. 680

18.4.2.1 Data Transfer Timing When CPHA = 0 ....................................... 680

18.4.2.2 Data Transfer Timing When CPHA = 1 ....................................... 681

18.4.3 Serial Clock Baud Rate .......................................................................... 682

18.4.4 Transfer Size ....................................................................................... 682

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