AEC-Q100车规级集成电路应力测试鉴定标准详解

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集成电路在汽车电子行业中扮演着至关重要的角色，其性能和可靠性直接关系到车辆的安全性和用户体验。AEC-Q100是美国汽车电子协会(Automotive Electronics Council, AEC)制定的一套针对车用电子组件的严格质量标准，特别是对于集成电路的应力测试资格认证。该标准于2003年7月18日发布，旨在确保车载电子元器件在极端环境条件下能够稳定工作，满足严苛的耐用性和安全性需求。 AEC-Q100应力测试鉴定包括多个关键环节： 1. **考核族定义** (Appendix 1): 这部分详细阐述了考核族的概念，即一组相似产品共享的测试和评估要求，确保所有成员都达到相同的质量水平。在集成电路的应力测试中，这可能涉及温度、电压、机械冲击等环境因素的模拟测试。 2. **设计、结构和考核的Q100证明** (Appendix 2): 提供了对设计过程、制造工艺以及最终测试结果的验证，确保产品在设计初期就考虑到潜在的应力影响，并在生产和质量控制阶段通过严格的测试程序。 3. **塑封体处理** (如附录3): 对于塑料封装的集成电路，可能需要特定的开包操作来进行键合或焊接测试，确保封装材料不会影响测试结果的准确性。 4. **最低要求的考核计划和结果** (Appendix 4): 明确了进行应力测试时所需的基本文件和数据，包括但不限于测试计划、执行过程记录、结果分析等，这些都是验证产品质量的重要依据。 5. **部分设计标准与电磁兼容性测试** (Appendix 5): 部分设计会根据这些标准来判断是否需要进行电磁兼容性(EMC)测试，以确保电路在复杂电磁环境中仍能正常运行。 **附件中的具体测试**: - **键合剪切测试** (AEC-Q100-001): 评估封装内键合连接的强度，确保在高应力下连接的稳定性。 - **人体模型静电放电测试** (AEC-Q100-002): 模拟人体接触产生的静电放电，测试集成电路对这种潜在故障源的抗扰动能力。 - **机器模式测试** (可能是机械冲击或振动测试，AEC-Q100-003): 确保电路在车辆运行过程中的机械应力下的性能。 AEC-Q100集成电路的应力测试鉴定是确保汽车电子设备在极端工况下可靠性的关键步骤，它涵盖了从设计到生产的各个环节，并通过各种专业测试确保产品能在严苛环境下正常工作。参与翻译此文档的人员为AEC-Q100标准在中国的推广和理解做出了重要贡献。

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods (continued)

TEST GROUP E – ELECTRICAL VERIFICATION TESTS

STRESS

ABV # NOTES

SAMPLE

SIZE / LOT

NUMBER

OF LOTS

CRITERIA

TEST

METHODS

ADDITIONAL REQUIREMENTS

Pre- and Post-Stress

Function/Parameter

压力试验前后的功能/参数

测试

TEST

H, P, B,

N, G

All

0 Fails Test program

to supplier

data sheet or

user

specification

Test is performed as specified in the

applicable stress reference and the additional

requirements in Table 2 and illustrated in

Figure 2. Test software used shall meet the

requirements of Q100-007. All electrical

testing before and after the qualification

stresses are performed to the limits of the

individual device specification in temperature

and limit value.

Electrostatic Discharge

Human Body Model /

Machine Model

放静电试验

HBM /

H, P, B,

See Test

Method

0 Fails 2KV

HBM 200V

AEC

Q100-002

Q100-003

TEST before and after ESD at room and hot

temperature. At least one of these models

must be performed. Device shall be classified

according to the maximum withstand voltage

level. Device levels <2000V HBM and/or

<200V MM require specific user approval.

Electrostatic Discharge

Charged Device Model

冲放电器件试验

CDM

H, P, B,

See Test

Method

0 Fails 750V

corner pins,

500V all other

pins

AEC

Q100-011

TEST before and after ESD at room

and hot temperature. Device shall be

classified according to the maximum withstand

voltage level. Device levels <750V corner pins

and/or <500V all other pins CDM require

specific user approval.

Latch-Up 闩锁试验

H, P, B,

6 1

0 Fails

AEC

Q100-004

See attached procedure for details on how to

perform the test. TEST before and after LU

at room and hot temperature.

Electrical Distributions

电分布试验

H, P, B,

30 3

CPK >1.33

>1.67

AEC

Q100-009

Supplier and user to mutually agree upon

electrical parameters to be measured. TEST

at room, hot, and cold temperature.

Fault Grading

---

--- ---

90%

AEC

Q100-007

For production testing, see section 4 of

Q100-007 for test requirements.

Characterization

特性试验

CHA

E7 --- --- ---

--- AEC Q003

To be performed on new technologies and

part families.

Electrothermally-Induced

Gate Leakage

热电门漏电流

D, P, B,

6 1

0 Fails

AEC

Q100-006

TEST before and after GL at room

temperature within 96 hours of GL stress

completion.

Electromagnetic

Compatibility

电磁相容性

EMC

E9 --- 1 1

<40dBuV

10KHz-1MHz

SAE J1752/3

– Radiated

Emissions

See Appendix 5 for guidelines on

determining the applicability of this test to the

device to be qualified. This test is performed

per agreement between user

and supplier on a case-by-case basis.

Page 13 of 28

AEC - Q100 - REV-F

J u ly 18, 2003

Automotive Electronics Council

Component Technical Committee

Table 2: Qualification Test Methods (continued)

TEST GROUP F – DEFECT SCREENING TESTS 缺陷甄别试验

STRESS

ABV # NOTES

SAMPLE

SIZE / LOT

NUMBER

OF LOTS

CRITERIA

TEST

REFERENCE

ADDITIONAL REQUIREMENTS

Process Average

Testing

过程平均试验

PAT

F1 --- --- --- ---

AEC Q001

Statistical

Bin/Yield Analysis

不良品统计分析

SBA

F2 --- --- --- ---

AEC Q002

It is highly desirable that the supplier adopt these tests in their standard

manufacturing operation. Performance of these tests offers opportunities

for sample size reduction per Table 2A.

TEST GROUP G – CAVITY PACKAGE INTEGRITY TESTS

STRESS

ABV # NOTES

SAMPLE

SIZE / LOT

NUMBER

OF LOTS

CRITERIA

TEST

REFERENCE

ADDITIONAL REQUIREMENTS

Mechanical Shock

机械冲击

H, D, G

39 3

0 Fails

JEDEC

JESD22 B104

Y1 plane only, 5 pulses, 0.5 msec duration, 1500 g peak acceleration.

TEST after CA.

Variable Frequency

Vibration

变频振动

VFV

H, D, G

39 3

0 Fails

JEDEC

JESD22 B103

20 Hz to 2 KHz to 20 Hz (logarithmic variation) in >4 minutes, 4X in each

orientation, 50 g peak acceleration. TEST after CA.

Constant

Acceleration

匀加速

H, D, G

39 3

0 Fails

MIL-STD-883

Method 2001

Y1 plane only, 30 K g-force for <40 pin packages, 20 K g-force for 40

pins and greater.

TEST before and after at room temperature.

Gross/Fine Leak

总

单独泄漏

GFL

H, D, G

39 3

0 Fails

MIL-STD-883

Method 1014

Any single-specified fine test followed by any single-specified gross test.

For ceramic packaged cavity devices only.

Package Drop

包装跌落试验

DROP

H, D, G

5 1

0 Fails

---

Drop part on each of 6 axes once from a height of 1.2m onto a concrete

surface. This test is for MEMS cavity devices only.

TEST before and after DROP at room temperature.

Lid Torque

盖扭矩

H, D, G

5 1

0 Fails

MIL-STD-883

Method 2024

For ceramic packaged cavity devices only.

Die Shear

芯片剪切

H, D, G

5 1

0 Fails

MIL-STD-883

Method 2019

To be performed before cap/seal for all cavity devices.

Internal Water

Vapor

内部水蒸汽

IWV

H, D, G

3 1

0 Fails

MIL-STD-883

Method 1018

For ceramic packaged cavity devices only.

AEC - Q100 - REV-F

J u ly 18, 2003

Page 14 of 28

Automotive Electronics Council

Component Technical Committee

Legend for Table 2

Notes: H Required for hermetic packaged devices only.

适用于密封式封装。

P Required for plastic packaged devices only.

适用于塑封。

B Required Solder Ball Surface Mount Packaged (BGA)

devices only.

适用于

BGA

。

N Nondestructive test, devices can be used to populate other tests or they can be used for production.

非破坏性试验。

D Destructive test, devices are not to be reused for qualification or production.破坏性试验。

S Required for surface mount plastic packaged devices only.适用于SMD。

G Generic data allowed. See section 2.3, Table 1, and Appendix 1.

适用于器件数据调用。

K Use method AEC-Q100-005 for preconditioning stand-alone Nonvolatile Memory integrated circuit or

an integrated circuit with an Nonvolatile Memory module.适用于预处理单机非易失性的存储芯片。

# Reference Number for the particular test.指明单独试验编号。

∗ All electrical testing before and after the qualification stresses are performed to the limits of the

individual device specification in temperature and limit value.

在应力试验前后所进行的电性能试验结果，均须符合器件的规定指标。

Table 2A: Part-Specific Qualification Sample Size / Lot Size Test Requirements

表

2A:

规定了

、

及

的具体器件的试验批次与样品数量

This table provides reduced lot and sample sizes for Qualification tests A1, A2, A3, A4, and B1 if the

indicated part specific information is available.

__The supplier shall have this information available for

customer review and approval.

Part Information

Part-specific testing has been performed

during manufacturing test

已在制造过程中完成的单项试验

Requirements for part

to be qualified

待考核批的要求

Characterization

Q003

特性试验

PAT

Q001

SBYA

Q002

批次/样品Lots / Samples per lot

for tests # A1

, A2, A3, A4, B1

X X X

1 /45

X X --

1 /45

X -- X

1 /45

X -- --

2/45

X X

1 /45

X --

2/45

-- --

2/45

-- -- -- 3/77

Notes: 1. The device was characterized in conformance with AEC Q003. 根据AEC Q300做特性试验。

2. Part Average Testing per AEC Q001 has been established for the part being qualified.

根据AEC Q100做器件平均试验。

3. Statistical Bin Yield Limits per AEC Q002 have been established for the part being qualified.

根据AEC Q002做良品统计试验。

4. Sample size for A1 equals the sum of sample sizes for A2, A3, and A4.

A1的取样大小适用于A2、A3及A4。

AEC - Q100 - REV-F

J u ly 18, 2003

Page 15 of 28

Appendix 1: Definition of a Qualification Family 附录1: 质量认证用术语

The qualification of a particular process will be defined within, but not limited to, the categories listed below. The

supplier will provide a complete description of each process and material of significance. There must be valid and

obvious links between the data and the subject of qualification.

以下的术语解释供了解但不属于唯一性解释. 供应商有其相应的名词释义, 术语与内容当有有机联长系.

For devices to be categorized in a qualification family, they all must share the same major process and materials

elements as defined below. All devices using the same process and materials are to be categorized in the same

qualification family for that process and are qualified by association when one family member successfully

completes qualification with the exception of the device specific requirements of section 4.2. Prior qualification data

obtained from a device in a specific family may be extended to the qualification of subsequent devices in that family.

对于待归于一类的器件, 它们应当有以下列明的相似的工艺流程与原材料成分. 对同一类器件,除在4.2.章节中需要测试

人个别项目外,可参照通用数据. 个别测出的结果也可充入通用数据库.

For broad changes that involve multiple attributes (e.g., site, materials, processes), refer to section A1.3 of this

appendix and section 2.3 of Q100, which allows for the selection of worst-case test vehicles to cover all the

possible permutations.

对多种因素待考核的器件, 应当选出条件最恶劣者作为考核批代表, 具体操作方法参照该附件的A1.3项,与Q100的2.3项.

A1.1

Fab Process

晶圆制程

Each process technology (e.g., CMOS, NMOS, Bipolar, etc.) must be considered and qualified separately.

No matter how similar, processes from one fundamental fab technology cannot be used for another. For

BiCMOS devices, data must be taken from the appropriate technology based on the circuit under

consideration.

充分考核黄素每一个操作工序(如: CMOS, NMOS, Bipolar等) 尽管采用多么相似的工艺,必须区分考核黄素各加工

单位的制作过程. 对于BiCMOS器件, 必须利用合适的流程保证数据采集的正确性.

Family requalification with the appropriate tests is required when the process or a material is changed (see

Table A1 for guidelines). The important attributes defining a qualification family are listed below:

(见表A1)对于工艺变更,用适当的试验项目来收集通用数据, 其中主要属性列举如下:

a. Wafer Fab Technology (e.g., CMOS, NMOS, Bipolar, etc.)

晶圆工艺 (如: CMOS, NMOS, Bipolar等)

b. Wafer Fab Process - consisting of the same attributes listed below:

晶圆制程- 共同属性如下:



Circuit element feature size (e.g., layout design rules, die shrinks, contacts, gates, isolations)

布线特征(如: layout design rules, die shrinks, contacts, gates, isolations)



Substrate (e.g., orientation, doping, epi, wafer size)

基板 (如: orientation, doping, epi, wafer size)

 Number of masks (supplier must show justification for waiving this requirement)

掩膜数量(supplier must show justification for waiving this requirement)

 Lithographic process (e.g., contact vs. projection, E-beam vs. X-ray, photoresist polarity)

刻蚀过程

(

如

: contact vs. projection, E-beam vs. X-ray, photoresist polarity)

 Doping process (e.g., diffusion vs. ion implantation) 掺杂过程(e.g., diffusion vs. ion implantation)



Gate structure, material and process (e.g., polysilicon, metal, salicide, wet vs. dry etch)

出入口结构,材料与工艺(e.g., polysilicon, metal, salicide, wet vs. dry etch)



Polysilicon material, thickness range and number of levels

多晶硅

厚度及层数



Oxidation process and thickness range (for gate and field oxides) 氧化工艺怀厚度 (for gate and field oxides)

 Interlayer dielectric material and thickness range 内层介电材料与厚度



Metallization material, thickness range and number of levels

金属层成份

厚度及层数



Passivation material and thickness range 钝化层成份厚度

 Die backside preparation process and metallization 芯片背面处理与金属层保护

Wafer Fab Site

晶圆加工地点

A1.2

Assembly Process - Plastic or Ceramic 组装批 – 塑封或陶瓷封装

The processes for plastic and ceramic package technologies must be considered and qualified separately.

For devices to be categorized in a qualification family, they all must share the same major process and

material elements as defined below. Family requalification with the appropriate tests is required when the

process or a material is changed. The supplier must submit technical justification to the user to support

the acceptance of generic data with pin (ball) counts, die sizes, substrate dimensions/material/thickness,

paddle sizes and die aspect ratios different than the device to be qualified.

塑料封装与陶瓷封装的考核应分开进行. 只有主要工艺相同者才能归于一类, 详情见下.除做恰当考核外,还需

用户确认封装技术指标与效果.

AEC - Q100 - REV-F

J u ly 18, 2003

Automotive Electronics Council

Component Technical Committee

Page 17 of 28

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