第六版《计算机组成原理：软件硬件接口》精华解析

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《计算机组成原理软件硬件接口英文版》（第六版）是一本备受赞誉的计算机科学教材，由业界专家们高度评价其在多个方面的出色表现。该书旨在提供一个全面且均衡的教育体验，将计算机组织原理与设计理论相结合，强调硬件与软件之间的交互作用，涵盖了当今信息技术领域的重要发展趋势。首先，作者对软件硬件接口的深入剖析是该书的核心内容。它探讨了如何在设计过程中平衡硬件和软件的需求，使两者协同工作，以实现系统的高效运行。第六版特别关注了RISC-V架构，这是一种开放源代码的指令集架构，它的兴起反映了现代计算机架构的多样性，以及对开源技术的重视。随着技术的进步，从传统的桌面计算到移动设备再到大数据处理，本书适时地更新了嵌入式处理器如ARM的相关知识，这些处理器在物联网和云计算等领域扮演着关键角色。新的内容突出了如何通过优化软件与硬件的协作来提升性能，这对于理解现代计算机系统的设计至关重要。对于新一代的学习者，特别是千禧一代，该书不仅保持了其经典的地位，而且在内容上与时俱进，适应了虚拟化和云计算的普及，以及对高性能计算和边缘计算的需求。书中深入浅出的讲解和严谨的理论基础，使其成为计算机架构学习者的理想参考书籍，无论是作为课堂教材还是个人自学资料，都能提供丰富的知识和实践经验。《计算机组成原理软件硬件接口英文版》（第六版）是一本融合了经典理论与前沿实践的宝典，它在保证学术深度的同时，注重实际应用和未来趋势，是任何对计算机架构感兴趣的读者不可多得的参考资料。无论是初学者还是经验丰富的专业人士，都可以从中收获宝贵的知识和洞见。

Preface

e most beautiful thing we can experience is the mysterious. It is the

source of all true art and science.

Albert Einstein, What I Believe, 1930

About This Book

We believe that learning in computer science and engineering should reect

the current state of the eld, as well as introduce the principles that are shaping

computing. We also feel that readers in every specialty of computing need

to appreciate the organizational paradigms that determine the capabilities,

performance, energy, and, ultimately, the success of computer systems.

Modern computer technology requires professionals of every computing

specialty to understand both hardware and soware. e interaction between

hardware and soware at a variety of levels also oers a framework for understanding

the fundamentals of computing. Whether your primary interest is hardware or

soware, computer science or electrical engineering, the central ideas in computer

organization and design are the same. us, our emphasis in this book is to show

the relationship between hardware and soware and to focus on the concepts that

are the basis for current computers.

e recent switch from uniprocessor to multicore microprocessors conrmed

the soundness of this perspective, given since the rst edition. While programmers

could ignore the advice and rely on computer architects, compiler writers, and silicon

engineers to make their programs run faster or be more energy-ecient without

change, that era is over. For programs to run faster, they must become parallel.

While the goal of many researchers is to make it possible for programmers to be

unaware of the underlying parallel nature of the hardware they are programming,

it will take many years to realize this vision. Our view is that for at least the next

decade, most programmers are going to have to understand the hardware/soware

interface if they want programs to run eciently on parallel computers.

e audience for this book includes those with little experience in assembly

language or logic design who need to understand basic computer organization as

well as readers with backgrounds in assembly language and/or logic design who

want to learn how to design a computer or understand how a system works and

why it performs as it does.

xvi Preface

About the Other Book

Some readers may be familiar with Computer Architecture: A Quantitative

Approach, popularly known as Hennessy and Patterson. (is book in turn is

oen called Patterson and Hennessy.) Our motivation in writing the earlier book

was to describe the principles of computer architecture using solid engineering

fundamentals and quantitative cost/performance tradeos. We used an approach

that combined examples and measurements, based on commercial systems, to

create realistic design experiences. Our goal was to demonstrate that computer

architecture could be learned using quantitative methodologies instead of a

descriptive approach. It was intended for the serious computing professional who

wanted a detailed understanding of computers.

A majority of the readers for this book do not plan to become computer

architects. e performance and energy eciency of future soware systems will

be dramatically aected, however, by how well soware designers understand the

basic hardware techniques at work in a system. us, compiler writers, operating

system designers, database programmers, and most other soware engineers

need a rm grounding in the principles presented in this book. Similarly,

hardware designers must understand clearly the eects of their work on soware

applications.

us, we knew that this book had to be much more than a subset of the material

in Computer Architecture, and the material was extensively revised to match the

dierent audience. We were so happy with the result that the subsequent editions

of Computer Architecture were revised to remove most of the introductory

material; hence, there is much less overlap today than with the rst editions of

both books.

Why RISC-V for This Edition?

e choice of instruction set architecture is clearly critical to the pedagogy of a

computer architecture textbook. We didn’t want an instruction set that required

describing unnecessary baroque features for someone’s rst instruction set, no

matter how popular it is. Ideally, your initial instruction set should be an exemplar,

just like your rst love. Surprisingly, you remember both fondly.

Since there were so many choices at the time, for the rst edition of Computer

Architecture: A Quantitative Approach we invented our own RISC-style instruction

set. Given the growing popularity and the simple elegance of the MIPS instruction

set, we switched to it for the rst edition of this book and to later editions of the

other book. MIPS has served us and our readers well.

It’s been 20 years since we made that switch, and while billions of chips that use

MIPS continue to be shipped, they are typically in found embedded devices where

the instruction set is nearly invisible. us, for a while now it’s been hard to nd a

real computer on which readers can download and run MIPS programs.

e good news is that an open instruction set that adheres closely to the RISC

principles has recently debuted, and it is rapidly gaining a following. RISC-V, which

was developed originally at UC Berkeley, not only cleans up the quirks of the MIPS

Preface xvii

instruction set, but it oers a simple, elegant, modern take on what instruction sets

should look like in 2017.

Moreover, because it is not proprietary, there are open-source RISC-V simulators,

compilers, debuggers, and so on easily available and even open-source RISC-V

implementations available written in hardware description languages. In addition,

there will soon be low-cost hardware platforms on which to run RISC-V programs.

Readers will not only benet from studying these RISC-V designs, they will be able

to modify them and go through the implementation process in order to understand

the impact of their hypothetical changes on performance, die size, and energy.

is is an exciting opportunity for the computing industry as well as for

education, and thus at the time of this writing more than 40 companies have joined

the RISC-V foundation. is sponsor list includes virtually all the major players

except for ARM and Intel, including AMD, Google, Hewlett Packard Enterprise,

IBM, Microso, NVIDIA, Oracle, and Qualcomm.

It is for these reasons that we wrote a RISC-V edition of this book, and we are

switching Computer Architecture: A Quantitative Approach to RISC-V as well.

Given that RISC-V oers both 32-bit address instructions and 64-bit address

instructions with essentially the same instruction set, we could have switched

instruction sets but kept the address size at 32 bits. Our publisher polled the faculty

who used the book and found that 75% either preferred larger addresses or were

neutral, so we increased the address space to 64 bits, which may make more sense

today than 32 bits.

e only changes for the RISC-V edition from the MIPS edition are those

associated with the change in instruction sets, which primarily aects Chapter2,

Chapter3, the virtual memory section in Chapter5, and the short VMIPS example

in Chapter6. In Chapter4, we switched to RISC-V instructions, changed several

gures, and added a few “Elaboration” sections, but the changes were simpler than

we had feared. Chapter1 and the rest of the appendices are virtually unchanged.

e extensive online documentation and combined with the magnitude of RISC-V

make it dicult to come up with a replacement for the MIPS version of Appendix

A (“Assemblers, Linkers, and the SPIM Simulator” in the MIPS Fih Edition).

Instead, Chapters 2, 3, and 5 include quick overviews of the hundreds of RISC-V

instructions outside of the core RISC-V instructions that we cover in detail in the

rest of the book.

Note that we are not (yet) saying that we are permanently switching to RISC-V. For

example, in addition to this new RISC-V edition, there are ARMv8 and MIPS versions

available for sale now. One possibility is that there will be a demand for all versions for

future editions of the book, or for just one. We’ll cross that bridge when we come to it.

For now, we look forward to your reaction to and feedback on this eort.

Changes for the Fifth Edition

We had six major goals for the h edition of Computer Organization and Design

demonstrate the importance of understanding hardware with a running example;

highlight main themes across the topics using margin icons that are introduced

xviii Preface

early; update examples to reect changeover from PC era to post-PC era; spread

the material on I/O throughout the book rather than isolating it into a single

chapter; update the technical content to reect changes in the industry since the

publication of the fourth edition in 2009; and put appendices and optional sections

online instead of including a CD to lower costs and to make this edition viable as

an electronic book.

Before discussing the goals in detail, let’s look at the table on the next page. It

shows the hardware and soware paths through the material. Chapters1, 4, 5, and

6 are found on both paths, no matter what the experience or the focus. Chapter1

discusses the importance of energy and how it motivates the switch from single

core to multicore microprocessors and introduces the eight great ideas in computer

architecture. Chapter2 is likely to be review material for the hardware-oriented,

but it is essential reading for the soware-oriented, especially for those readers

interested in learning more about compilers and object-oriented programming

languages. Chapter 3 is for readers interested in constructing a datapath or in

learning more about oating-point arithmetic. Some will skip parts of Chapter3,

either because they don’t need them, or because they oer a review. However, we

introduce the running example of matrix multiply in this chapter, showing how

subword parallels oers a fourfold improvement, so don’t skip Sections 3.6 to 3.8.

Chapter4 explains pipelined processors. Sections 4.1, 4.5, and 4.10 give overviews,

and Section 4.12 gives the next performance boost for matrix multiply for those

with a soware focus. ose with a hardware focus, however, will nd that this

chapter presents core material; they may also, depending on their background,

want to read Appendix A on logic design rst. e last chapter, on multicores,

multiprocessors, and clusters, is mostly new content and should be read by

everyone. It was signicantly reorganized in this edition to make the ow of

ideas more natural and to include much more depth on GPUs, warehouse-scale

computers, and the hardware–soware interface of network interface cards that

are key to clusters.

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