PIC16F1824: PIC系列单片机详细指南

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"这篇文档是关于PIC系列单片机中的PIC16F1824型号的生产批准过程报告，提供了详细的PPAP（生产部分批准流程）信息，该报告适用于英文阅读者。" 正文: PIC系列单片机是由Microchip Technology公司生产的微控制器单元（MCU），广泛应用于各种嵌入式系统设计中。PIC系列以其高效能、低功耗和易于编程的特点而闻名。PIC16F1824是这个家族中的一款，尤其适合在需要精简指令集计算（RISC）架构的小型应用中使用。该报告是针对PIC16F1824 IN14L DTS-SOP封装的Level 4 PPAP，表明产品已通过了第四版PPAP手册所规定的全部评估流程。PPAP是汽车行业的一个关键质量控制程序，确保产品的设计、制造过程和材料都能满足客户的预期和规格要求。Level 4的PPAP通常涉及更严格的验证，包括对设计记录、过程能力、现场运行试验等方面的深入评估。报告在2011年4月4日完成，并在2013年4月10日和12月进行了更新。它包含了根据PPAP手册结构划分的不同部分，用户可以通过左侧的书签快速导航到相关文档的首页。其中，BillofMaterials（BOM，物料清单）详细列出了用于定制Microchip part number的特定制造流程，强调了订购时必须使用在PSW（生产零件批准工作单）上指定的定制MCU型号，以确保PPAP的完整性和有效性。 Microchip Technology的质量体系符合ISO/TS-16949标准，这是全球汽车供应链中普遍接受的质量管理体系，同时也满足特定客户的要求。若未返回带有有效签名的PSW，但订购了PSW上列出的产品，这将被视为对报告中信息的接受和批准。总体而言，这份报告为开发者和制造商提供了关于PIC16F1824的详细质量保证信息，帮助他们在项目中选择和使用这款单片机时，确保其合规性和可靠性。在使用或采购PIC16F1824之前，了解这份PPAP报告对于理解该器件的制造过程和质量标准至关重要。

OPERATIONS

Design planning is the process by which

design plans are established and used by the

cross-functional teams to track critical project

milestones. These teams are composed of

design personnel and a designated cross-

functional Product Development Team consisting

of members from areas including quality, test,

marketing, applications and manufacturing.

Design Objective Specifications (DOS) document

the product design inputs. Review sessions

are conducted throughout the design process

to ensure that the DOS, as well as designs,

continue to meet all requirements.

The design validation process commences with

Manufacturing Review. This process outlines

tasks necessary for product development.

These tasks include the establishment of

characterization plans, test plans, qualification

plans, process description, product schedules,

validation plans, verification to quality

conformance requirements, process steps, test

procedures, and review of the compatibility of

the design to production processes. Product/

process development outputs also include:

 Designation of special characteristics

 Development of FMEAs

 Establishment of actions to reduce

potential failure modes with higher risk

priority numbers

 Development of control plans to identify

critical process steps and their associated

control specifications

Final reviews of simulation data, as well as

device performance data, are conducted

to determine if the product meets the

requirements of the product specification.

The reviews are held by the cross-functional

Product Development Team before the product

is released for first silicon manufacturing. After

“first silicon,” design validation is performed

to ensure that product conforms to defined

user needs and/or requirements. The intent of

this process is to ensure that products meet

specified requirements and that all quality

related activities are identified, planned for and

implemented. The resulting product plan is

documented through the Product Specification

Index (PSI).

Manufacturing Process

Once the product design and process have been

successfully validated, the product is formally

released to production. The generic wafer

fabrication, assembly and test flow is illustrated

in Figure 6. Specifications are maintained (and

are under revision control) for all fabrication,

assembly and test operations.

The wafer fabrication process consists of

several sub-processes. The general process

is as follows: A layer of oxide is grown on the

surface of a silicon wafer. Because the oxide

can be removed by etching, it provides a tool

for placing patterns (mask) onto the wafer and

selectively introducing the dopants required

by the specific device. After oxidation, a photo

resist chemical is dispensed on the wafer. The

wafer is aligned with the mask and exposed

to ultra-violet light to produce a pattern on the

wafer. The wafer is ‘etched’ to leave specific

areas of exposed silicon for implantation of

dopants to a prescribed concentration and

profiles. Dopants are further diffused into

the wafer by placing the wafers in furnaces

where heat is applied. A deposition process is

used to deposit a thin film of specific material

over the wafer for the purpose of isolation,

planarization, providing a conductive layer, or

adding a protective layer. The sub-process cycle

is repeated several times, depending on the

device under fabrication. The final fabrication

operation involves putting a protective seal

over the circuit by depositing a thin coating

of material over the entire wafer surface. The

completed wafers are sent to Map and Probe

for wafer level testing (failed die are identified).

After test, the wafers are packed and sent for

package assembly and test.

During assembly, individual good and bad die

are separated. Once the package type has

been determined, the die is attached to an

appropriate carrier (e.g., leadframe paddle for

plastic packages). The device is then processed

through wire bond, where thin wires of gold or

aluminum are used to connect the die bonding

pads to the package leads. Packages are then

sealed with a lid or molding compound and

marked with the part number and other product

identifiers. The packages are processed through

electrical test, quality control sample test and

OPERATIONS

final visual inspection to verify functional and

visual/mechanical performance. SPC monitors,

tests and inspections are utilized throughout

the manufacturing process to ensure process

control and product performance requirements

have been met. A reliability monitor system

is used to verify product and process design

stability over time.

Qualification System

Microchip’s qualification process is directed

at ensuring that new products are evaluated,

characterized and qualified per specified

requirements. The process provides a statistical

basis to determine and validate the levels

of expected quality and reliability. As inputs

to the process come from several functions

of the organization, the qualification process

is conducted in a cross-functional team

environment. The team operates using a fully

documented qualification process which sets

forth guidelines for standard qualifications,

monitoring and sampling procedures. A set

of baseline specifications is maintained that

states which changes require re-qualification.

These process changes can only be made

after successful demonstration of reliability

performance. This procedure results in a reliable

field performance, while enabling the smooth

phase-in of improved designs and product

capability.

Listed below are the types of qualification

tests typically performed to confirm product

performance to design objectives. Also provided

is a brief description of test purpose and

method/conditions. Detailed testing procedures

and acceptance criteria are documented in

Microchip’s worldwide quality conformance

specification.

WAFER FAB

Mask, Etch Diffusion,

Metallization, etc.

WAFER LEVEL TEST

Map/Probe

WAFER LEVEL

PACK/SHIP

PACKAGE ASSEMBLY

Wafer Saw, Die Attach

Wire Bond, Sealing,

Mark

FINAL TEST

FINAL VISUAL

INSPECTION

PACK

• In-line SPC Monitors

• Visual/Auto Inspections

• 'Ship Worthiness' Verification

• 100 percent Electrical Test

• QC Sample Test

• Visual Inspection of Pack

• In-line SPC Monitors

• Visual Inspections

• Parametric Electrical Test

• Wafer level Functional Test

• Trend Analysis

SHIP

Figure 6: General Wafer

Fabrication, Assembly

and Test Flow

Die Tests Test Purpose Method/Condition

Dynamic

Life Test

To demonstrate the reliability

of devices subjected to the

speciﬁ ed conditions over

extended periods of time.

MIL-STD-883, method 1005. Devices are exercised at the

maximum data sheet operating voltage. Two temperature/duration com-

binations are used. Devices subjected to 125°C are functionally tested

at 168 hours (infant) and 1008 hours (long term). Devices subjected to

150°C are functionally tested at 96 hours (infant) and 408 hours (long

term). Sample: 600(0) for new processes and products, 200(0) for any

process change on an existing process.

ESD To categorize the electrostatic

discharge sensitivity for micro-

circuits.

MIL-STD-883, notice 8, method 3015 for HBM.

EIA/JESD22-A115-A waveform with MIL-STD-883, method 3015

combinations for MM. Corporate Guidelines are 2000V-HBM and

200V-MM. Sample: 12-HBM, 12-MM (3 per voltage level).

Endurance

Cycle

(EEPROM/

FLASH)

All EEPROM/Flash memory

designs require a sufﬁ cient

number of endurance cycles in

page, type, block or bulk mode

to meet device requirements.

MIL-STD-883, method 1033. Cycling at 85°C, devices

subjected to 100K page/byte cycles or 100K page/block/bulk cycles

depending upon the device endurance speciﬁ cation. Sample: 231(0).

Latch-Up

Test

To categorize the latch-up

susceptibility for all micro-

circuits.

QCI-30521. Corporate Guidelines of greater than 200mA (+ and -) at

25°C and 100mA (+ and -) at the highest rated operating tempera-

ture.

Retention

Bake

To examine the possible loss

of data in programmed device.

MIL-STD-883, method 1033. Two temperature/duration combinations

are used. Devices subjected to 150°C are tested at 168 hours and

1008 hours. Devices subjected to 175°C are tested at 96 hours and

504 hours. Sample: 200(0).

OPERATIONS

Package Tests Test Purpose Method/Condition

Bond Strength

To ensure that lead bonded devices

meet established lead bond strength

limits and to ensure that no bond

degradation occurs during the sealing

process.

MIL-STD-883, method 2011, C or D. Devices are subjected to

simulated seal cycle using a heater plate and preseal units are

pulled (2 grams for Aluminum and 3 grams for gold – 0.001”

diameter wire). Sample: 15(0).

Coplanarity

To verify the coplanarity of leads. QCI-33003. Lead > 4mils out of common plane is considered fail.

Sample: 30(0).

Endpoint Electrical

To determine device functionality. Devices are tested to electrical test specifications.

HAST

To determine the effects of high

temperature and high humidity on

package.

JESD22-A110. Devices tested are subjected to 130

°C, 85%

RH, and maximum data sheet operating voltage. After 96

hours the devices are functionally tested at 25°C and hot

temperature. Sample: 77(0).

Operating Life

(DLT)

To demonstrate the reliability of devices

subjected to specified conditions over an

extended time period.

MIL-STD-883, method 1005. Devices are exercised at the maximum

data sheet operating voltage. Conditions are 150

°C for 408 hours

with full functional test at -40°C, 25°C and 125°C after 408

hours. Sample: 600(0).

Physical

Dimensions

To verify that the external physical

dimensions of the device conform to

drawing dimensions.

JESD22-B100. Dimensions verified for body, lead length, space

between leads, etc. Sample: 2(0).

Pressure Cooker

To sample electrically good packages

which have been molded and moisture

impregnated at the same time.

JESD22-A102. Devices placed in pressure cooker and exposed

to conditions of 121.5

°C, 15PSIG pressure 100% RH for 96

hours – functionally test at 25°C. Sample: 77(0).

Lead Finish

To determine the integrity of all primary

and undercoat lead finish.

MIL-STD-883, method 2025. A bend stress is applied to randomly

selected leads from each device. Sample: 15(0).

Lead Integrity

To check the resistance of the leads to

metal fatigue.

JESD22-B105, condition A/C. Devices are subjected to 3 bend

stress cycles, followed with a visual inspection. Sample: 45 leads

from a min. of 5 devices.

Solderability

To evaluate the solderability of

terminations that are joined by

soldering.

JESD22-B102. Specimens are immersed in flux and dipped in a

245

°C, ±5°C molten solder bath. Sample: 22(0).

Temperature Cycle

To determine the resistance of a part

exposure at extremes of high and

low temperatures and to the effect of

alternate exposures to these extremes.

JESD22-A104 condition C. Devices are subjected to 500 thermal

cycles alternating between -65

°C and +150°C. Sample: 77(0).

Visual

To perform a visual inspection of the

device for visual/mechanical criteria.

PI-91081B. Devices are inspected for defects or damage to case,

leads or seals, or illegible markings. Sample: 22(0).

Note: Older devices may have been qualified under different conditions/criteria relevant at the time of qualification.

OPERATIONS

Ongoing Reliability

Once qualified, Microchip employs a reliability

monitor system to verify that the level of

quality and reliability demonstrated during the

qualification of product is being maintained

over time.

Listed below are the types of monitor tests

typically performed to confirm continued product

performance attributes. These are accelerated

tests that evaluate performance well beyond

the typical application conditions. The test

methods and conditions are equivalent to those

performed during qualification.

Occasionally tests are combined to create

sequential tests (commonly used reliability

tests executed one after another using the

same devices). Microchip performs sequential

testing to simulate the interaction of worst

case environmental condition experienced

in field applications. Surface-mount devices

are preconditioned (bake, moisture soak,

convection reflow) prior to the package

tests to accurately emulate the assembly

process performed by customers. As a result,

Microchip’s reliability monitor data provides a

clear indication of expected field reliability.

Test

Test Method

and Condition Conditions Minimum Sample Size

Sample/

Testing

Frequency

Lead Integrity JB105, condition

A/C

45 leads from a minimum of 5

devices

Weekly

Lead Finish MIL 2003 45 leads from a minimum of 5

devices

Weekly

Temperature Cycle

Electrical Test

JESD22-A014

PDC – S12/14/16

-65°C to 150°C, 100 cycles

25°C

77 Weekly

Solderability JESD22-B102 245°C solder 120 leads or 5 parts Weekly

HAST

Electrical Test

JESD22-A110

PDC – S12/14/16

130°C/85% RH,

maximum data sheet

operating voltage for 96

hours

25°C

77 Weekly

Pressure Cooker

Electrical Test

JESD22-A102

PDC – S12/14/16

121.5°C, 15 PSIG

pressure 100% RH for 96

hours

25°C

77 Weekly

Dynamic Life Test MIL-STD-883,

method 1005

150°C for 408 hours.

Devices are exercised at

the maximum data sheet

operating voltage.

Depends upon hardware Weekly

Endurance Cycle MIL-STD-883,

method 1033

100K cycles at 85°C Depends upon hardware Weekly

Retention Bake MIL-STD-883,

method 1033

175°C for 504 hours 100 Weekly

OPERATIONS

Reliability Data – High Temperature Dynamic

Life Test (DLT)

Microchip’s products provide competitive

leadership in reliability with demonstrated

performance of less than 100 FITs (Failures-

in-Time) operating life for most products.

High temperature DLT (150°C) accelerates

random failure modes which would occur in

user applications. In addition to an elevated

temperature, voltage bias and functional signals

are used to exercise the device in a manner

similar to user systems. The actual failure rate

experienced could be considerably less than

that calculated if lower device temperatures

occur in the application board.

Detailed Microchip product reliability reports are

published quarterly and are available through

Microchip’s web site.

Reliability Data – High Temperature Data

Retention Bake (RET)

Microchip’s products provide competitive

leadership in reliability with demonstrated

performance of less than 100 FITs (Failures-

in-Time) operating life for most products. In

data retention bake, devices are subjected to

175°C bake. This bake accelerates charge loss

in the memory cell, and 96 hours at 175°C is

equivalent to greater than 250 years in the field

at 55°C. The actual failure rate experienced

could be considerably less than that calculated

if lower device temperatures occur in the

application board.

Detailed Microchip product reliability reports are

published quarterly and are available through

Microchip’s web site.

Total Endurance™ Software

Endurance is the measure of the number

of times an EEPROM can be erased and

rewritten. Since differing criteria are

often used by suppliers when determining

EEPROM endurance, it is important that the

specific conditions of the study used in this

determination be well understood. Unfortunately,

the conditions used rarely fit the application

being used by the customer. As a result, the

actual EEPROM endurance performance in

the application may not meet the data book

specification or the customer’s requirements.

The task of determining the true “in application”

endurance prior to implementation becomes

guesswork.

Microchip has developed a way to eliminate this

guesswork. Through an extensive examination

of technology, application and environmental

conditions, Microchip has developed a software

model capable of accurately predicting EEPROM

endurance. This Windows®based endurance

prediction tool, called Total Endurance

™

software,

allows the user of the software to perform a

“what if” analysis of their application and fine

tune their design to achieve established reliability

requirements. Trade-offs can be examined for

several variables. These variables include: device

type, voltage, temperature, cycling mode, data

pattern, number of bytes/cycles, erase/write

cycles per day, application life and PPM. These

variables have been chosen because they can be

directly modified by the customer. The model uses

these inputs to generate numerical and graphical

outputs of the endurance characteristics for the

conditions provided.

The model itself was developed from the results

of a comprehensive 2

7-4

factorial experiment

conducted by a cross-functional team of

Microchip engineers. A comparison of model

data to endurance data taken from reliability

monitors of Microchip’s EEPROM products

showed a good fit between curves.

The Total Endurance

™

software is available from

local sales representatives, distributors and the

Microchip web site.

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