AFE5818：16通道超声模拟前端，低噪声与高采样率ADC

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TI-AFE5818是一款高性能的模拟前端集成电路，专为无线通信应用设计，具备16个独立通道的功能，旨在提供卓越的信号处理性能。该芯片的主要特点包括： 1. **低功耗与高灵敏度**： AFE5818具有140毫瓦每通道的功耗，这意味着在保持高性能的同时，能有效管理电源消耗。其噪声性能出色，拥有0.75nV/√Hz的输入噪声，有助于确保信号的清晰度。 2. **多模式ADC选项**：提供两种不同分辨率的模数转换器（ADC），包括14位65 MSPS和12位80 MSPS，满足不同应用场景对采样速度的需求，提供了灵活性。 3. **集成模拟前端组件**：包括低噪声放大器(LNA)，可编程增益选项（24dB, 18dB, 12dB），线性输入范围覆盖0.25VPP、0.5VPP和1VPP，以及可编程有源终端，这些都增强了信号的接收能力。 4. **压控衰减器(VCAT)**： VCAT功能可实现40dB的动态范围调整，允许用户根据需要优化信号路径的增益控制。 5. **可编程增益放大器(PGA)**：提供两种选择，24dB和30dB的增益，进一步扩展了信号处理的动态范围，确保了信号在整个频率范围内的一致性。 6. **超声波模拟前端设计**： AFE5818采用16通道的全模拟前端架构，包括混频器，实现了连续波(CW)无源混频，为信号处理提供高效解决方案。 7. **滤波器与信号链路**：配备了3rd-Order LPF滤波器，支持多种带宽选项，如10, 15, 20, 30, 35, 和 50MHz，能够有效抑制噪声和干扰。 8. **接口选项**：支持SPIIN、SPIOUT、LVDS等多种接口，便于与其他系统组件连接，且有1XCLK和16XCLK时钟选项，提高了系统时序的灵活性。 9. **产品支持和服务**： TI提供了技术文档、工具与软件支持，以及样本和购买服务，确保用户可以顺利应用到安全关键或其他复杂应用领域。值得注意的是，使用该产品时，必须阅读末尾的重要通知，了解产品可用性、保修政策、安全关键应用使用限制、知识产权声明以及其他相关免责声明。这是一份生产数据资料，英文版本为SBAS687，最后更新日期为2015年2月修订于8月。

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AFE5818

ZHCSDE6B –FEBRUARY 2015–REVISED AUGUST 2015

www.ti.com.cn

Electrical Characteristics (continued)

At T

= 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, ac-

coupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V,

LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC

resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency f

5 MHz, and output amplitude V

OUT

= –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across

the full temperature range.

PARAMETER TEST CONDITION MIN TYP MAX UNIT

CW DOPPLER

en (RTI) Input voltage noise (CW)

1 channel mixer, LNA = 24 dB, 500-Ω external feedback resistor 0.98

nV/√Hz

16 channel mixers, LNA = 24 dB, 32-Ω external feedback resistor 0.31

1 channel mixer, LNA = 18 dB, 500-Ω external feedback resistor 1.31

16 channel mixers, LNA = 18 dB, 32-Ω external feedback resistor 0.5

(RTO)

Output voltage noise

(CW)

1 channel mixer, LNA = 24 dB, 500-Ω external feedback resistor 13.3

nV/√Hz

16 channel mixers, LNA = 24 dB, 32-Ω external feedback resistor 3.56

1 channel mixer, LNA = 18 dB, 500-Ω external feedback resistor 8.85

16 channel mixers, LNA = 18 dB, 32-Ω external feedback resistor 2.86

NF Noise figure

= 100 Ω, R

= high-Z, f

= 2 MHz, 1 channel, LNA = 18 dB 3.18

= 100 Ω, R

= high-Z, f

= 2 MHz, 16 channels, LNA = 18 dB 6.15

CW operating range CW signal carrier frequency 8 MHz

CWCLK CW clock frequency

CLKP_1X, CLKM_1X (16X mode) 8

MHzCLKP_16X, CLKM_16X (16X mode) 128

CLKP_16X, CLKM_16X (4X mode) 32

Clock amplitude

(ac-coupled)

CLKM_1X, CLKP_1X and CLKM_16X, CLKP_16X 0.2 0.35 V

CLK duty cycle 1X and 16X CLKs 35% 65%

Common-mode voltage Internally provided 2.5 V

CMOS

CMOS input clock

amplitude

4 5 V

CW mixer conversion

loss

4 dB

CW mixer phase noise

1 kHz off 2-MHz carrier (16X mode, 1 channel) 156

dBc/Hz

1 kHz off 2-MHz carrier (16X mode, 16 channel) 161

DR Input dynamic range Input frequency = 2.5 MHz

LNA = 24 dB 159.1

dBFS/HzLNA = 18 dB 162.6

LNA = 12 dB 164.4

IMD3 Intermodulation distortion

= 5 MHz, f

= 5.01 MHz, both tones at –16-dBm amplitude,

16 channels summed up in-phase, CW feedback resistor = 32 Ω

–50

dBc

= 5 MHz, f

= 5.01 MHz, both tones at –16-dBm amplitude,

single channel summed up in-phase, CW feedback resistor = 500 Ω

–60

I/Q channel gain

matching

16X mode ±0.04

4X mode ±0.04

I/Q channel phase

matching

16X mode ±0.01

Degrees

4X mode ±0.01

Image rejection ratio –50 dBc

AFE5818

ZHCSDE6B –FEBRUARY 2015–REVISED AUGUST 2015

www.ti.com.cn

Electrical Characteristics (continued)

At T

= 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, ac-

coupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V,

LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC

resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency f

5 MHz, and output amplitude V

OUT

= –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across

the full temperature range.

PARAMETER TEST CONDITION MIN TYP MAX UNIT

POWER DISSIPATION (continued)

TGC mode

(Total power dissipation

per channel)

TGC low-noise mode, no signal

ADC in 12-bit resolution,

80 MSPS

143 170

mW/Ch

ADC in 14-bit resolution,

65 MSPS

140

ADC in 14-bit resolution,

50 MSPS

136

ADC in 14-bit resolution,

40 MSPS

134

TGC low-noise mode, 500-mV

input,1% duty cycle 139.5

TGC medium-power mode 104.4

TGC medium-power mode, 500-mV

input, 1% duty cycle 107.4

TGC low-power mode 93.5

TGC low-power, 500-mV

input, 1% duty cycle 96

CW mode

(Total power dissipation

per channel with ADC

and PGA in power-down

state)

CW mode, no signal, ADC shutdown CW mode

16X clock = 32 MHz 80

mW/Ch

16X clock = 80 MHz 95 112

CW mode, 16X clock = 80 MHz, CW summing amplifier external feedback

resistance = 33 Ω, 500-mV

input to all 16 channels, ADC shutdown

203

AVDD_3P3 current

TGC low-noise mode, no signal 414 467

TGC medium-power mode, no signal 260

TGC low-power mode, no signal 207

CW mode, no signal

16X clock = 32 MHz 285

16X clock = 80 MHz 285 337

TGC low-noise mode, 500-mV

input, 1% duty cycle 430

TGC medium-power mode, 500-mV

input, 1% duty cycle 274

TGC low-power mode, 500-mV

input, 1% duty cycle 219

CW mode, 16X clock = 80 MHz, 500-mV

input to all 16 channels 740

AVDD_5V current

TGC low-noise, medium-power, or low-power mode, no signal 57 80

CW mode, no signal

16X clock = 32 MHz 64

16X clock = 80 MHz 115 136

TGC, low-noise, medium-power, or low-power mode, 500-mV

input,

1% duty cycle

CW mode, 16X clock = 80 MHz, 500-mV

input to all 16 channels 160

AVDD_1P8 current

12-bit mode

80 MSPS 170 197

20 MSPS 120

14-bit mode

65 MSPS 160

20 MSPS 120

DVDD_1P2 current

12-bit mode

80 MSPS 110 160

20 MSPS 50

14-bit mode

65 MSPS 95

20 MSPS 52

DVDD_1P8 current

12-bit mode

80 MSPS 100 132

20 MSPS 85

14-bit mode

65 MSPS 95

20 MSPS 85

AFE5818

www.ti.com.cn

ZHCSDE6B –FEBRUARY 2015–REVISED AUGUST 2015

Electrical Characteristics (continued)

At T

= 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, ac-

coupled with a 0.1-µF capacitor at INP, 15-nF capacitor to ground at INM, no active termination, VCNTLP = VCNTLM = 0 V,

LNA = 18 dB, PGA = 24 dB, LPF filter = 15 MHz, low-noise mode, internal 500-Ω CW feedback resistor, 14-bit ADC

resolution, ADC_CLKP and ADC_CLKM = 50-MHz differential, LVDS mode to capture ADC data, input signal frequency f

5 MHz, and output amplitude V

OUT

= –1 dBFS, unless otherwise noted. Minimum and maximum values are specified across

the full temperature range.

PARAMETER TEST CONDITION MIN TYP MAX UNIT

(3) The PSRR value in dBc is measured with respect to the supply tone amplitude applied at the device supply (that is, 100 mV

POWER-DOWN

Power dissipation in

power-down mode

Partial power-down when PDN_FAST = high (1.8 V) 28

mW/Ch

Complete power-down when PDN_GBL = high (1.8 V) 2.2

Power-down response

time

1 µs

Power-up response time

Partial power-down when PDN_FAST= high (1.8 V) and the device in partial

power-down time for < 500 µs

3 µs

Complete power-down when PDN_GBL = high (1.8 V) 2.7 ms

PSMR

Power-supply modulation

ratio

= 5 MHz, supply tone of 100 mV

1-kHz frequency

AVDD_3P3 –65

dBc

AVDD_5V –63

PSRR

Power-supply rejection

ratio

(3)

Supply tone of 100 mV

at 1-kHz frequency

AVDD_3P3 –70

dBc

AVDD_5V –70

(1) All LVDS specifications are characterized but are not tested at production.

8.6 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. Typical values are at T

= 25°C, minimum and maximum values are across the full temperature range of

MIN

= -40°C to T

MAX

= 85°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8 =

1.8 V, external differential load resistance between the LVDS output pair, and R

LOAD

= 100 Ω, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LOAD RESISTANCE

External differential load resistance Between LVDS output pair 100 Ω

CMOS DIGITAL INPUTS (PDN_GBL, PDN_FAST, RESET, SCLK, SDIN, SEN)

High-level input voltage 1.4 2.1 V

Low-level input voltage 0 0.3 V

High-level input current 100 µA

Low-level input current 100 µA

Input capacitance 4 pF

LVDS DIGITAL OUTPUTS (DOUTPx, DOUTMx)

(1)

| Output differential voltage 420 mV

Output offset voltage

Common-mode voltage of DOUTPx and

DOUTMx

1.03 V

CMOS DIGITAL OUTPUT (SDOUT)

High-level output voltage 1.4 DVDD_1P8 V

Low-level output voltage DVSS 0.3 V

Output impedance 50 Ω

AFE5818

ZHCSDE6B –FEBRUARY 2015–REVISED AUGUST 2015

www.ti.com.cn

(1) See Figure 1.

(2) All LVDS specifications are characterized but are not tested at production.

(3) The specification for the minimum data valid window is larger than the sum of the minimum setup and hold times because there can be

a skew between the ideal transitions of the serial output data with respect to the transition of the bit clock. This skew can vary across

channels and across devices. A mechanism to correct this skew can therefore improve the setup and hold timing margins. For example,

the LVDS_DCLK_DELAY_PROG control can be used to shift the relative timing of the bit clock with respect to the data.

(4) TX_TRIGD is the internally delayed version of TX_TRIG that gets latched on the rising edge of the ADC clock.

(5) t

CLKIN

is the ADC clock period in nanoseconds (ns).

8.7 Output Interface Timing

Typical values are at T

= 25°C, AVDD_1P8 = 1.8 V, AVDD_3P3 = 3.3 V, AVDD_5V = 5 V, DVDD_1P2 = 1.2 V, DVDD_1P8

= 1.8 V, differential ADC clock, LVDS load C

LOAD

= 5 pF, R

LOAD

= 100 Ω, 14-bit ADC resolution, and sample rate = 65 MSPS,

unless otherwise noted. Minimum and maximum values are across the full temperature range of T

MIN

= –40°C to T

MAX

= 85°C.

MIN TYP MAX UNIT

GENERAL

Aperture delay

(1)

1.6 ns

δt

Aperture delay variation from device to device

(at same temperature and supply)

±0.5 ns

APJ

Aperture jitter with LVPECL clock as input clock 0.5 ps

Wake-up time

Time to valid data after exiting

standby mode

(units are in number of ADC_CLKP,

ADC_CLKM cycles)

15 Cycles

Time to valid data after exiting

PDN_GBL mode

1 ms

Time to valid data after stopping and

restarting the input clock

100 µs

ADC TIMING

ADC latency

Default after reset

(1)

8.5

ADC clocks

Low-latency mode 4.5

LVDS TIMING

(2)

Frame clock frequency

(1)

CLKIN

MHz

FRAME

Frame clock duty cycle 50%

SER

Number of bits serialization of each ADC word 12 16 Bits

Output rate of

serialized data

1X output data rate mode N

SER

× f

CLKIN

1000

Mbps

2X output data rate mode 2 × N

SER

× f

CLKIN

1000

Bit clock frequency f

/ 2 500 MHz

BIT

Bit clock duty cycle 50%

Data bit duration

(1)

1 1000 / f

PDI

Clock propagation delay

(1)

6 × t

+ 5 ns

δt

PROP

Clock propagation delay variation from device to device

(at same temperature and supply)

±2 ns

ORF

DOUT, DCLK, FCLK rise and fall time, transition time

between –100 mV and +100 mV

0.2 ns

OSU

Minimum serial data, serial clock setup time

(1)

/ 2 – 0.4 ns

Minimum serial data, serial clock hold time

(1)

/ 2 – 0.4 ns

Minimum data valid window

(3)(1)

– 0.65 ns

TX_TRIG TIMING

TX_TRIG_DEL

Delay between TX_TRIG and TX_TRIGD

(4)

0.5 0.4 × t

CLKIN

(5)

SU_TX_TRIGD

Setup time related to latching TX_TRIGD relative to the

rising edge of the system clock

0.6 ns

H_TX_TRIGD

Hold time related to latching TX_TRIGD relative to the

rising edge of the system clock

0.4 ns

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