汽车应用 LIN 收发器TLIN2024A-Q1技术规格

175 浏览量更新于2024-06-28 4 收藏 2.45MB PDF 举报

"TI-TLIN2024A-Q1.pdf" TI-TLIN2024A-Q1是一款专为汽车应用设计的四通道Local Interconnect Network (LIN) 收发器，符合AEC-Q100 Grade 1标准，确保在苛刻的汽车环境中具有高可靠性。这款芯片支持LIN 2.0、LIN 2.1、LIN 2.2、LIN 2.2A以及ISO/DIS 17987-4的电气物理层（EPL）规范，同时也符合SAE J2602-1 LIN网络标准。该器件具备功能安全能力，提供了帮助进行功能安全系统设计的相关文档。它可以适应12伏和24伏的电池应用，支持最高20千比特每秒的LIN发送数据速率和高达100千比特每秒的接收数据速率。其操作电源电压范围广泛，从4伏到48伏，适应性强。 TLIN2024A-Q1集成有45千欧的LIN上拉电阻，并且在电源开启和关闭时提供无干扰的LIN总线和RXD输出操作。在节能方面，它具有睡眠模式，能实现超低电流消耗，可通过LIN总线或EN引脚的本地唤醒事件进行唤醒。保护特性是该器件的另一大亮点，包括对LIN总线的±60伏故障容忍度、电源欠压保护、TXD主导状态超时保护（DTO）、热关断保护，以及在无电源或接地断开时的系统级安全运行。所有这些特性都封装在一个3.5毫米×5.5毫米的VQFN封装中，优化了自动光学检测，有利于组装和制造过程。总体而言，TI-TLIN2024A-Q1是汽车电子系统中实现高效、安全、可靠LIN通信的理想选择，其高性能和多种保护机制确保了在复杂汽车环境中的稳定运行。

7.6 Electrical Characteristics (continued)

parameters valid across -40℃ ≤ T

≤ 125℃ (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LIN dominant low-level output voltage

(3)

TXD = low, 7 V ≤ V

SUP

≤ 48 V 0.2 V

SUP

LIN dominant low-level output voltage

(1)

(2)

TXD = low, 7 V ≤ V

SUP

≤ 18 V 0.2 V

SUP

LIN dominant low-level output voltage

(3)

TXD = low, 4 V ≤ V

SUP

< 7 V 1.2 V

SUP_NON_OP

SUP

where impact of recessive LIN bus

< 5% (ISO/DIS 17987 Param 11)

TXD & RXD open, LIN = 4 V to 58 V –0.3 58 V

BUS_LIM

Limiting current (ISO/DIS 17987 Param

57)

TXD = 0 V, V

LIN

= 48 V, R

MEAS

= 440 Ω,

SUP

= 48 V, V

BUSdom

< 4.518 V

75 120 300 mA

BUS_PAS_dom

Receiver leakage current, dominant

(ISO/DIS 17987 Param 13)

LIN = 0 V, V

SUP

= 24 V Driver off/

recessive; See Figure 8-6

–2 mA

BUS_PAS_rec1

Receiver leakage current, recessive

(ISO/DIS 17987 Param 14)

LIN > V

SUP

, 8 V ≤ V

SUP

≤ 48 V, Driver

off; See Figure 8-7

20 µA

BUS_PAS_rec2

Receiver leakage current, recessive

(ISO/DIS 17987 Param 14)

LIN = V

SUP

, Driver off; See Figure 8-7 –5 5 µA

BUS_NO_GND

Leakage current, loss of ground

(ISO/DIS 17987 Param 60)

GND = V

SUP

, 0 V ≤ V

LIN

< 36 V, V

SUP

24 V; Figure 8-8

–2 2 mA

leak gnd(dom)

Leakage current, loss of ground

(5)

SUP

= 8 V, GND = open, V

SUP

= 18 V,

GND = open

Commander

= 1 kΩ, C

= 1 nF

Responder

= 20 kΩ, C

= 1 nF

LIN = dominant

–1 1 mA

leak gnd(rec)

Leakage current, loss of ground

(5)

SUP

= 8 V, GND = open, V

SUP

= 18 V,

GND = open

Commander

= 1 kΩ, C

= 1 nF

Responder

= 20 kΩ, C

= 1 nF

LIN = recessive

-100 100 µA

BUS_NO_BAT

Leakage current, loss of supply

(ISO/DIS 17987 Param 61)

0 V ≤ V

LIN

≤ 48 V, V

SUP

= GND;

See; Figure 8-9

5 µA

BUSdom

Low level input voltage (ISO/DIS 17987

Param 62)

(3)

LIN dominant (including LIN dominant

for wake-up); See Figure 8-4 and Figure

8-3

0.4 V

SUP

BUSrec

High level input voltage (ISO/DIS 17987

Param 63)

(3)

LIN recessive; See Figure 8-4 and

Figure 8-3

0.6 V

SUP

LIN recessive high-level input voltage

(1)

(2)

7 V ≤ V

SUP

≤ 18 V 0.47 0.6 V

SUP

LIN dominant low-level input voltage

(1)

(2)

7 V ≤ V

SUP

≤ 18 V 0.4 0.53 V

SUP

BUS_CNT

Receiver center threshold (ISO/DIS

17987 Param 64)

BUS_CNT

= (V

BUSdom

+ V

BUSrec

)/2 See

Figure 8-4 and Figure 8-3

0.475 0.5 0.525 V

SUP

HYS

Hysteresis voltage (ISO/DIS 17987

Param 65)

HYS

= (V

BUSrec

- V

BUSdom

) See Figure

8-4 and Figure 8-3

0.175 V

SUP

HYS

Hysteresis voltage (SAE J2602)

HYS

= V

- V

See Figure 8-4 and

Figure 8-3

0.07 0.175 V

SUP

SERIAL_DIODE

Serial diode LIN termination pullup path I

SERIAL_DIODE

= 10 μA 0.4 0.7 1 V

Pullup resistor to V

SUP

(ISO/DIS 17987

Param 26)

Normal and Standby modes 20 45 60 kΩ

RSLEEP

Pullup current source to V

SUP

Sleep mode, V

SUP

= 27 V, LIN = GND –20 –2 µA

LINPIN

Capacitance of the LIN pin V

SUP

= 14 V 25 pF

(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ

(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω

(3) ISO 17987 bus load conditions (C

LINBUS

, R

LINBUS

) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.

(4) RXD uses open drain output structure therefore V

level is based upon microcontroller supply voltage V

(5) I

leak gnd

= (V

BAT

- V

LIN

)/R

Load

www.ti.com

TLIN2024A-Q1

SLLSFM7 – JUNE 2022

Submit Document Feedback

Product Folder Links: TLIN2024A-Q1

(6) Values are for each V

SUP

7.7 Duty Cycle Characteristics

parameters valid across -40℃ ≤ T

≤ 125℃ (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

12V

Duty Cycle 1 (ISO/DIS 17987 Param

27)

(3)

REC(MAX)

= 0.744 x V

SUP

DOM(MAX)

= 0.581 x V

SUP

, V

SUP

= 7 V to 18 V, t

BIT

= 50 µs (20 kbps), D1 = t

BUS_rec(min)

/(2 x

BIT

) (See Figure 8-10, Figure 8-11)

0.396

12V

Duty Cycle 1

(3)

(4)

REC(MAX)

= 0.625 x V

SUP

, TH

DOM(MAX)

= 0.581 x V

SUP

, V

SUP

= 4 V to 7 V, t

BIT

= 50 µs (20 kbps), D1 = t

BUS_rec(min)

/(2 x

BIT

) (See Figure 8-10, Figure 8-11)

0.396

D1 Duty Cycle 1

(1)

(2)

(4)

REC(MAX)

= 0.744 x V

SUP

DOM(MAX)

= 0.581 x V

SUP

= 7 V to 18 V, t

BIT

= 52 μs

D1 = t

BUS_rec(min)

/(2 x t

BIT

) (See Figure

8-10, Figure 8-11)

0.396

12V

Duty Cycle 2 (ISO/DIS 17987 Param

28)

(3)

REC(MIN)

= 0.422 x V

SUP

, TH

DOM(MIN)

= 0.284 x V

SUP

, V

SUP

= 7 V to 18 V, t

BIT

= 50 µs (20 kbps), D2 = t

BUS_rec(MAX)

/(2

x t

BIT

) (See Figure 8-10, Figure 8-11)

0.581

12V

Duty Cycle 2

(3)

(4)

REC(MIN)

= 0.546 x V

SUP

, TH

DOM(MIN)

= 0.4 x V

SUP

, V

SUP

= 4 V to 7 V, t

BIT

50 µs (20 kbps), D2 = t

BUS_rec(MAX)

/(2 x

BIT

) (See Figure 8-10, Figure 8-11)

0.581

D2 Duty Cycle 2

(1)

(2)

(4)

REC(MIN)

= 0.422 x V

SUP

DOM(MIN)

= 0.284 x V

SUP

= 7 V to 18 V, t

BIT

= 52 μs

D2 = t

BUS_rec(MAX)

/(2 x t

BIT

) (See Figure

8-10, Figure 8-11)

0.581

12V

Duty Cycle 3 (ISO/DIS 17987 Param

29)

(3)

REC(MAX)

= 0.778 x V

SUP

, TH

DOM(MAX)

= 0.616 x V

SUP

, V

SUP

= 7 V to 18 V, t

BIT

= 96 µs (10.4 kbps), D3 = t

BUS_rec(min)

/(2

x t

BIT

) (See Figure 8-10, Figure 8-11)

0.417

12V

Duty Cycle 3

(3)

(4)

REC(MAX)

= 0.645 x V

SUP

, TH

DOM(MAX)

= 0.616 x V

SUP

, V

SUP

= 4 V to 7 V, t

BIT

96 µs (10.4 kbps), D3 = t

BUS_rec(min)

/(2 x

BIT

) (See Figure 8-10, Figure 8-11)

0.417

D3 Duty Cycle 3

(1)

(2)

(4)

REC(MAX)

= 0.778 x V

SUP

DOM(MAX)

= 0.616 x V

SUP

= 7 V to 18 V, t

BIT

= 96 μs

D3 = t

BUS_rec(min)

/(2 x t

BIT

) (See Figure

8-10, Figure 8-11)

0.417

12V

Duty Cycle 4 (ISO/DIS 17987 Param

30)

(3)

REC(MIN)

= 0.389 x V

SUP

, TH

DOM(MIN)

= 0.251 x V

SUP

, V

SUP

= 7 V to 18

V, t

BIT

= 96 µs (10.4 kbps), D4 =

BUS_rec(MAX)

/(2 x t

BIT

) (See Figure 8-10,

Figure 8-11)

0.59

12V

Duty Cycle 4

(3)

(4)

REC(MIN)

= 0.422 x V

SUP

, TH

DOM(MIN)

= 0.284 x V

SUP

, V

SUP

= 4 V to 7 V, t

BIT

96 µs (10.4 kbps), D4 = t

BUS_rec(MAX)

/(2

x t

BIT

) (See Figure 8-10, Figure 8-11)

0.59

D4 Duty Cycle 4

(1)

(2)

(4)

REC(MIN)

= 0.389 x V

SUP

DOM(MIN)

= 0.251 x V

SUP

= 7 V to 18 V, t

BIT

= 96 μs

D4 = t

BUS_rec(MAX)

/(2 x t

BIT

) (See Figure

8-10, Figure 8-11)

0.59

TLIN2024A-Q1

SLLSFM7 – JUNE 2022

www.ti.com

8 Submit Document Feedback

Product Folder Links: TLIN2024A-Q1

剩余38页未读，继续阅读

不觉明了

粉丝: 4516
资源: 5759

汽车应用 LIN 收发器TLIN2024A-Q1技术规格

TI-TLIN2024-Q1.pdf

TI-TLIN2022A-Q1.pdf

TI-TLIN1029A-Q1.pdf

TI-TLIN1024A-Q1.pdf

TI-TLIN1022A-Q1.pdf

TI-TLIN2021A-Q1.pdf

TI-TLIN2029A-Q1.pdf

TI-TLIN1021A-Q1.pdf

TI-TLIN1022-Q1.pdf

TI-TLIN2027-Q1.pdf

最新资源