VESA发布DisplayPort 1.4标准：灵活接口，提升视频传输与外设连接

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DP1.4标准是VESA（Video Electronics Standards Association）提出的DisplayPort（DP）规范的最新版本，它于2015年11月3日发布。该标准的主要目的是设计一种灵活的系统和设备，能够在数字通信接口上实现视频、音频和其他数据在源设备（如计算机或显示器）与 sink 设备（如投影仪、电视或 DVD 播放器）之间的传输，适用于内部连接（如计算机内部接口）以及外部显示器连接。在VESA Proposed DisplayPort 1.4 d1标准中，对先前版本（如DPv1.1和DPv1.2）进行了修订和完善。在DPv1.1的修订版中，主要纠正了错误并提供了更清晰的说明，以提升标准的准确性。DPv1.2引入了一系列增强功能，包括更高的传输速度、更加灵活的拓扑管理、单个连接支持多流传输、高速辅助通道通信等，这些都是为了适应现代电子设备的高效率需求。此标准定义了一个开放的数字接口，不仅限于PC和显示器之间的连接，还包括扩展到其他设备组合，如PC与投影仪、PC与电视，以及像DVD播放器与电视这样的多媒体设备。这使得兼容 DisplayPort 的设备能够无缝集成，提供高质量的视频和音频传输，同时支持多种标准和格式，以满足不同应用场景的需求。 DisplayPort 1.4 d1标准还关注电源管理，允许通过单一连接同时传输视频信号和电源，简化了设计和部署，减少了线缆和附件的复杂性。此外，该标准还包含关于数据安全和知识产权保护的规定，确保数据传输的隐私和版权不受侵犯。总结来说，VESA Proposed DisplayPort 1.4标准是一个高度可扩展且功能强大的技术规范，它促进了电子设备之间的高效连接，提升了用户体验，并且为未来的显示技术发展奠定了基础。随着科技的进步，DisplayPort将继续演化，以满足不断变化的市场需求和用户期待。

VESA Proposed DisplayPort (DP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.4 d1

Table L-1: Sample Display Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .859

Table M-1: Main Contributor History (Previous Versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .861

DRAFT

VESA Proposed DisplayPort (DP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.4 d1

Figures

Figure 1-1: DisplayPort Data Transport Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 1-2: Layered Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 2-1: Overview of Link Layer Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 2-2: Single DP Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 2-3: DP Source Device-to-DP Sink Device via a DP Repeater . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 2-4: DP Source Device-to-Legacy Sink via DP-to-Legacy Converter . . . . . . . . . . . . . . . . . . . .68

Figure 2-5: Legacy Source Device-to-DP Sink Device via a Legacy-to-DP Converter . . . . . . . . . . . .68

Figure 2-6: Multiple DP Source Devices-to-DP Sink Device via an Input Switch . . . . . . . . . . . . . . . .68

Figure 2-7: DP Source Device to Multiple DP Sink Devices via a DP Replicator . . . . . . . . . . . . . . . .69

Figure 2-8: High-Level Block Diagram of DPTX Main-Link Data Path . . . . . . . . . . . . . . . . . . . . . . .72

Figure 2-9: High-Level Block Diagram of DPRX Main-Link Data Path . . . . . . . . . . . . . . . . . . . . . . .73

Figure 2-10: Main Video Stream Data Packing Example for a 4-Lane Main-Link. . . . . . . . . . . . . . . . .77

Figure 2-11: Link Symbols over the Main-Link without Main Video Stream . . . . . . . . . . . . . . . . . . . .80

Figure 2-12: VB-ID, Mvid7:0, and Maud7:0 Packing over the Main-Link. . . . . . . . . . . . . . . . . . . . . . .81

Figure 2-13: Transfer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Figure 2-14: Secondary-Data Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Figure 2-15: Inter-Lane Skewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Figure 2-16: Reference Pulse and Feedback Pulse of Stream Clock Regeneration Circuit. . . . . . . . . .123

Figure 2-17: Mvid and Nvid Value Determination Example in

Asynchronous Clock Mode in a Source Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Figure 2-18: Transport of DisplayPort Main Stream Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Figure 2-19: Video Horizontal Blanking Expansion Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Figure 2-20: Interlaced Video Format/Timing for Odd Number of Lines per Frame . . . . . . . . . . . . . .133

Figure 2-21: Interlaced Video Format/Timing for Even Number of Lines per Frame . . . . . . . . . . . . .133

Figure 2-22: INFOFRAME SDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Figure 2-23: Audio_TimeStamp SDP Mapping over Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Figure 2-24: Audio_Stream SDP over Main-Link for 2-Channel Layout Audio . . . . . . . . . . . . . . . . .155

Figure 2-25: Audio_Stream SDP over Main-Link for 8-Channel Layout Audio . . . . . . . . . . . . . . . . .157

Figure 2-26: Audio_Stream SDP over Main-Link for 16-Channel Layout Audio

(3D LPCM Audio Extension Type Code 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Figure 2-27: Audio_Stream SDP over Main-Link for 32-Channel Layout Audio

(3D LPCM Audio Extension Type Code 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

Figure 2-28: Audio_Stream SDP over Main-Link for DST Audio Layout . . . . . . . . . . . . . . . . . . . . . .167

Figure 2-29: 3D LPCM Audio Data Allocation with Audio INFOFRAME Byte 4 = FEh,

8.1 SPM Asserted (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Figure 2-30: 3D LPCM Audio Data Allocation with Audio INFOFRAME Byte 4 = FFh,

8.1 SPM Asserted RCD Order Used (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Figure 2-31: 3D LPCM Audio Data Allocation with Audio INFOFRAME Byte 4 = FEh,

All SPM Asserted (Informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Figure 2-32: 3D LPCM Audio Data Allocation with Audio INFOFRAME Byte 4 = FFh,

All SPM Asserted RCD Order Used (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

DRAFT

VESA Proposed DisplayPort (DP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.4 d1

Figure 2-33: Data Mapping within the 4-Byte Payload of an Audio_Stream SDP

with IEC 60958-like Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Figure 2-34: Data Mapping within the 4-Byte Payload of an Audio_Stream SDP

with One Bit Audio Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Figure 2-35: Data Mapping within the 4-Byte Payload Sub-layout of a DST Audio_Stream SDP

with DST Audio Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

Figure 2-36: Audio_CopyManagement SDP over the Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Figure 2-37: ISRC SDP over the Main-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Figure 2-38: Pixel Pattern Representation for Pixel Interleaved Method . . . . . . . . . . . . . . . . . . . . . . .190

Figure 2-39: Interleave Pattern Corresponding to 2-way Interleaved Stereo

where Right Image Pixels are on Even Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 2-40: Interleave Pattern Corresponding to a Checkerboard Pattern

with Alternating Left and Right Image Pixels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Figure 2-41: Side-by-Side Stereo Format with Left View followed by Right View . . . . . . . . . . . . . . .191

Figure 2-42: Field Sequential Stereo Format with Left View and Right View

Indicated via MISC1 Field, bits 2:1, of the MSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Figure 2-43: Stacked Top, Bottom Stereo Format with Left View

on Top and Right View on Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Figure 2-44: VSC SDP over the Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193

Figure 2-45: Extension SDP Mapping over the Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

Figure 2-46: Camera SDP Mapping over the Main-Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Figure 2-47: Camera RAW Active Pixels (Main Video Stream) and Camera SDP Transport . . . . . . .201

Figure 2-48: PPS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Figure 2-49: PPS SDP Payload Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

Figure 2-50: VSC_EXT_VESA SDP Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 2-51: SDP Splitting in SST Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Figure 2-52: Block Diagram of an RS (15:13) Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Figure 2-53: ECC Block Nibble-Interleaving for 2- and 4-Lane Main-Links . . . . . . . . . . . . . . . . . . . .212

Figure 2-54: ECC Block Nibble-Interleaving for a 1-Lane Main-Link . . . . . . . . . . . . . . . . . . . . . . . . .212

Figure 2-55: ECC Block Nibble-Interleaving for 2- and 4-Lane Main-Links (Header) . . . . . . . . . . . .213

Figure 2-56: ECC Block Nibble-Interleaving for a 1-Lane Main-Link (Header) . . . . . . . . . . . . . . . . .213

Figure 2-57: Makeup of 15 Nibble Code-Word for Packet Payload . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Figure 2-58: Makeup of 15 Nibble Code-Word for Packet Header . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Figure 2-59: AUX CH DPTX State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216

Figure 2-60: AUX CH DPRX State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Figure 2-61: DisplayPort Data Transport Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

Figure 2-62: DP Multi-Stream Transport. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Figure 2-63: Illustration of Virtual Channel, Link, and Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

Figure 2-64: Single-Stream Source Device to Dual-Stream Sink Devices (Dual-Display Clone) . . . .226

Figure 2-65: Dual-Stream Source Devices to Dual-Stream Sink Devices (Extended Desktop) . . . . . .226

Figure 2-66: SST-only Isochronous Transport Service Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

Figure 2-67: MST Isochronous Transport Service Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228

Figure 2-68: Sideband CH Communication Layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

Figure 2-69: Branching Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

Figure 2-70: MST Multi-Sink Device with Multiple Main Stream Sinks and SDP Sinks . . . . . . . . . .234

Figure 2-71: MST Sink Device with Single Main Stream Sink and Multiple SDP Sinks. . . . . . . . . . .235

Figure 2-72: MST Audio-only Sink Device with SDP Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

DRAFT

VESA Proposed DisplayPort (DP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.4 d1

Figure 2-73: Example MST Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

Figure 2-74: Example Topology with RAD of Devices Relative to Source Devices . . . . . . . . . . . . . .238

Figure 2-75: MST Topology with a Loop and a Parallel Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

Figure 2-76: Layers Covered in this Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

Figure 2-77: Logical Block Diagram of MST DP Source Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

Figure 2-78: Logical Block Diagram of MST DP Sink Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Figure 2-79: Logical Block Diagram of MST DP Branch Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Figure 2-80: Logical Block Diagram of SST DP Source Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

Figure 2-81: Logical Block Diagram of SST DP Sink Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

Figure 2-82: Multi-function Branch-Sink Device Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

Figure 2-83: Example Multi-function MST Branch-Sink Device Enumeration . . . . . . . . . . . . . . . . . .252

Figure 2-84: Enumeration after DP SST Monitor 1 Plugged. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

Figure 2-85: DSC Decompression Operation Control by way of Virtual/Physical DPCD Register Setting

254

Figure 2-86: Link Timing Generation in MST Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

Figure 2-87: Time Slot Allocation to VC Payload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259

Figure 2-88: VC Payload Symbol Generator of a DP Source Device . . . . . . . . . . . . . . . . . . . . . . . . . .260

Figure 2-89: 4-Symbol Sequence Unit Mapping to Main-Link Lanes . . . . . . . . . . . . . . . . . . . . . . . . .261

Figure 2-90: Repetition of 4-Symbol Sequence Unit Example for 1-Lane Main-Link . . . . . . . . . . . . .261

Figure 2-91: AV Stream Mapping in MST Mode After VC Payloads for a Given Main Video

Stream are Concatenated and VC Payload Fill Symbol Sequences Removed . . . . . . . . .265

Figure 2-92: DP Source Device VC Payload Mapping Logical Block Diagram. . . . . . . . . . . . . . . . . .266

Figure 2-93: DP Sink Device VC Payload Mapping Logical Block Diagram. . . . . . . . . . . . . . . . . . . .266

Figure 2-94: Pass-through DP Branch Device VC Payload Mapping Logical Block Diagram. . . . . . .266

Figure 2-95: SDP Splitting in MST Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269

Figure 2-96: Bandwidth Management by Payload Bandwidth Manager . . . . . . . . . . . . . . . . . . . . . . . .271

Figure 2-97: ACT Allocation Change Trigger Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

Figure 2-98: VC Payload Allocation Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

Figure 2-99: Example Time Sequence for Adding a New Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

Figure 2-100: Timing Sequence for Adding a New Payload with Error . . . . . . . . . . . . . . . . . . . . . . . . .287

Figure 2-101: Timing Sequence for Deleting a Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

Figure 2-102: Timing Sequence for Deleting a Payload with an Error . . . . . . . . . . . . . . . . . . . . . . . . . .289

Figure 2-103: Timing Sequence for Deleting a Payload with Locally Unrecoverable Error. . . . . . . . . .290

Figure 2-104: Timing Sequence for Reducing the VC Payload Allocation. . . . . . . . . . . . . . . . . . . . . . .291

Figure 2-105: Timing Sequence for Increasing the VC Payload Allocation . . . . . . . . . . . . . . . . . . . . . .292

Figure 2-106: MSTM ECF and LVP Signaling at Link Frame Boundary. . . . . . . . . . . . . . . . . . . . . . . .301

Figure 2-107: ECF Immediately Prior to ACT Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

Figure 2-108: DisplayPort Layer Architecture Model with Compression. . . . . . . . . . . . . . . . . . . . . . . .302

Figure 2-109: High-Level Compression Architectural Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302

Figure 2-110: Initial Discovery, Setup and Enable of DSC Compression. . . . . . . . . . . . . . . . . . . . . . . .303

Figure 2-111: Compressed/Uncompressed Stream Indication in VB-ID. . . . . . . . . . . . . . . . . . . . . . . . .305

Figure 2-112: Example of Packing DSC Data Bytes within a Video Frame . . . . . . . . . . . . . . . . . . . . . .308

Figure 2-113: Examples of AUX CH Bridging Two I

C Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318

Figure 2-114: Action Flow Sequences of the Source upon HPD Event (Informative) . . . . . . . . . . . . . .354

Figure 2-115: Messaging AUX Client in DP Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486

Figure 2-116: Messaging AUX Client Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .488

DRAFT

VESA Proposed DisplayPort (DP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED Version 1.4 d1

Figure 2-117: Down Request Message and Down Reply Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . .489

Figure 2-118: Up Request Message and Up Reply Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .489

Figure 2-119: Mapping Message Transaction to Multiple Sideband MSGs

(SB MSG CRC Is the Sideband_MSG_Data_CRC Field) . . . . . . . . . . . . . . . . . . . . . . . .500

Figure 2-120: RAD Update Along the Path Using Example Topology. . . . . . . . . . . . . . . . . . . . . . . . . .509

Figure 2-121: AUX Error While Delivering a Down Req Message . . . . . . . . . . . . . . . . . . . . . . . . . . . .516

Figure 2-122: AUX Error While Delivering an Up Req Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .517

Figure 2-123: Source Device Delay Aggregation and Introduction of Delay Stamps. . . . . . . . . . . . . . .539

Figure 2-124: DisplayPort Monitor Connected through a Repeater Device . . . . . . . . . . . . . . . . . . . . . .541

Figure 2-125: Delay Compensation for Audio-to-Video Synchronization . . . . . . . . . . . . . . . . . . . . . . .542

Figure 2-126: DisplayPort Source Streaming Audio-to-Video Streams to Multiple Monitors . . . . . . . .543

Figure 2-127: Delay Compensation for Audio-to-Video Sync in a Multi-Monitor Configuration . . . . .544

Figure 2-128: Delay Compensation for Audio-to-Audio Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .546

Figure 2-129: GTC Value Measurement Point by GTC Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550

Figure 2-130: Lock Acquisition and Maintenance Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551

Figure 2-131: AUX Transactions for GTC Synchronization (Informative). . . . . . . . . . . . . . . . . . . . . . .557

Figure 3-1: DP PHY Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .562

Figure 3-2: Compliance Measurement Points of the Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .566

Figure 3-3: Compliance Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .566

Figure 3-4: HBR2 Upstream Device Compliance Test Configuration . . . . . . . . . . . . . . . . . . . . . . . .568

Figure 3-5: HBR2 Downstream Device Compliance Test Configuration . . . . . . . . . . . . . . . . . . . . . .569

Figure 3-6: HBR Upstream Device Compliance Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . .570

Figure 3-7: HBR Downstream Device Compliance Test Configuration . . . . . . . . . . . . . . . . . . . . . . .570

Figure 3-8: HBR Tethered Downstream Device Compliance Test Configuration . . . . . . . . . . . . . . .571

Figure 3-9: RBR Upstream Device Compliance Test Configuration. . . . . . . . . . . . . . . . . . . . . . . . . .572

Figure 3-10: RBR Downstream Device Compliance Test Configuration . . . . . . . . . . . . . . . . . . . . . . .572

Figure 3-11: RBR Tethered Downstream Device Compliance Test Configuration . . . . . . . . . . . . . . .573

Figure 3-12: Definition of Differential Voltage and Differential Voltage Peak-to-Peak. . . . . . . . . . . .574

Figure 3-13: Example of Pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .576

Figure 3-14: Character to Symbol Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .578

Figure 3-15: AUX CH Differential Pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .585

Figure 3-16: Self-clocking with Manchester-II Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .585

Figure 3-17: AUX CH SYNC Pattern and STOP Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .586

Figure 3-18: AUX CH EYE Mask at Connector Pins of TX Device. . . . . . . . . . . . . . . . . . . . . . . . . . .589

Figure 3-19: AUX CH EYE Mask at Connector Pins of RX Device. . . . . . . . . . . . . . . . . . . . . . . . . . .590

Figure 3-20: Clock Recovery Sequence of Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .604

Figure 3-21: Channel Equalization Sequence of Link Training. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608

Figure 3-22: POST_LT_ADJ_REQ Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610

Figure 3-23: FEC Encoding in DPTX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .613

Figure 3-24: FEC Decoding in DPRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614

Figure 3-25: Schematic RS Encoder Representation (INFORMATIVE) . . . . . . . . . . . . . . . . . . . . . . .615

Figure 3-26: Interleaved FEC Block Transport for 1-lane Configuration . . . . . . . . . . . . . . . . . . . . . . .617

Figure 3-27: Interleaved FEC Block Transport for 2- and 4-lane Configurations. . . . . . . . . . . . . . . . .617

Figure 3-28: Two-way FEC Interleaving for 1-lane Configuration in DPTX . . . . . . . . . . . . . . . . . . . .618

Figure 3-29: Two-way FEC Interleaving for 1-lane Configuration in DPRX . . . . . . . . . . . . . . . . . . . .618

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