TRF7960A多协议13.56MHz RFID读写器IC技术规格

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"TI-TRF7960A是一款由德州仪器(TI)推出的13.56MHz RFID读写器集成电路，集成了多种RFID协议处理，适用于各种安全访问和无线通信应用。" TI的TRF7960A是一款高度集成的射频识别(RFID)读写器芯片，它支持多个国际标准和协议，包括ISO/IEC15693、ISO/IEC18000-3、ISO/IEC14443A、ISO/IEC14443B、NFC论坛的设备类型2至5以及FeliCa™技术。这款芯片的设计旨在提供灵活且高效能的解决方案，适用于多种应用场景，如安全访问控制、产品认证、数字门锁、公共交通票务、医疗系统以及远程传感器应用。在硬件特性方面，TRF7960A的工作电压范围宽泛，从2.7VDC到5.5VDC，可以根据不同系统需求进行配置。输出功率可编程，最高可达+20dBm（100mW）或+23dBm（200mW），以适应不同的通信距离和环境。同时，该芯片还支持可编程的I/O电压电平，范围在1.8VDC至5.5VDC之间，以兼容各种电压级别的微控制器和其他接口设备。此外，它还提供了可编程的系统时钟频率输出（RF，RF/2，RF/4）和调制深度，以优化通信性能。 TRF7960A的接收器部分采用了双接收器架构，具备接收信号强度指示器(RSSI)，可以有效防止“读取漏洞”，并检测邻近读取器或环境中的噪声。对于低功耗系统设计，它提供了可编程的功耗模式，关断状态下电流消耗低于0.5µA，这对于电池供电或能量采集的应用非常有利。该芯片还集成了一个电压稳压器，为微控制器提供稳定电源，确保系统稳定性。在接口方面，TRF7960A支持并行和串行外设接口(SPI)，便于与各种微控制器进行通信。其封装形式为32引脚的QFN封装，尺寸仅为5mm×5mm，适合紧凑型设计。工作温度范围广泛，可在-40°C至110°C之间稳定运行。 TRF7960A是一款高度集成的多功能RFID读写器芯片，具备广泛的协议支持、灵活的电源管理、出色的接收性能和低功耗特性，使得它成为各种智能卡系统、无线通信及物联网(IoT)应用的理想选择。开发者可以利用这些特性来构建高效、可靠的13.56MHz RFID解决方案，满足不同行业的定制化需求。

TRF7960A

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By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 250 mV below

VIN, but not higher than 5 V for VDD_RF and 3.4 V for VDD_A and VDD_A. The "Delta Voltage" in

automatic regulator mode can be increased up to 400 mV (for more details, see bits B0 to B2 in register

0x0B).

Power Amplifier Supply: VDD_PA

The power amplifier of the TRF7960A is supplied through VDD_PA (pin 4). The positive supply pin for the

RF power amplifier is externally connected to the regulator output VDD_RF (pin 3).

I/O Level Shifter Supply: VDD_I/O

The TRF7960A has a separate supply input VDD_I/O (pin 16) for the build in I/O level shifter. The

supported input voltage ranges from 1.8 V to VIN, however not exceeding 5.5 V. Pin 16 is used to supply

the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical

applications, VDD_I/O is directly connected to VDD_X while VDD_X also supplies the MCU. This ensures

that the I/O signal levels of the MCU match with the logic levels of the TRF7960A.

Negative Supply Connections: VSS, VSS_RX, VSS_A, VSS_PA

The negative supply connections VSS_X of each functional block are all externally connected to GND.

The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic

negative supply is VSS_D (pin 29), the RF output stage negative supply is VSS_PA (pin 6), and the

negative supply for the RF receiver VSS_RX (pin 7).

6.4 Supply Regulator Settings

The input supply voltage mode of the reader must be selected. This is done in the Chip Status Control

configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply

voltage is below 4.3 V, the 3-V configuration should be used.

The various regulators can be configured to operate in automatic or manual mode. This is done in the

Regulator and I/O Control register (0x0B) (see Table 6-1 and Table 6-2).

Table 6-1. Supply Regulator Setting: 5-V System

ADDRESS

OPTION BITS SETTING IN REGULATOR CONTROL

(1)

COMMENTS

B7 B6 B5 B4 B3 B2 B1 B0

Automatic Mode (default)

0B 1 x x x x x 1 1 Automatic regulator setting with 250-mV difference

0B 1 x x x x x 1 0 Automatic regulator setting with 350-mV difference

0B 1 x x x x x 0 0 Automatic regulator setting with 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 VDD_RF = 5 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.4 V, VDD_X = 3.4 V

TRF7960A

ZHCS266F –JUNE 2011 –REVISED MAY 2017

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Table 6-2. Supply Regulator Setting: 3-V System

ADDRESS

OPTION BITS SETTING IN REGULATOR CONTROL

(1)

COMMENTS

B7 B6 B5 B4 B3 B2 B1 B0

Automatic Mode (default)

0B 1 x x x x x 1 1 Automatic regulator setting with 250-mV difference

0B 1 x x x x x 1 0 Automatic regulator setting with 350-mV difference

0B 1 x x x x x 0 0 Automatic regulator setting with 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 VDD_RF = 3.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 1 1 0 VDD_RF = 3.3 V, VDD_A = 3.3 V, VDD_X = 3.3 V

0B 0 x x x x 1 0 1 VDD_RF = 3.2 V, VDD_A = 3.2 V, VDD_X = 3.2 V

0B 0 x x x x 1 0 0 VDD_RF = 3.1 V, VDD_A = 3.1 V, VDD_X = 3.1 V

0B 0 x x x x 0 1 1 VDD_RF = 3.0 V, VDD_A = 3.0 V, VDD_X = 3.0 V

0B 0 x x x x 0 1 0 VDD_RF = 2.9 V, VDD_A = 2.9 V, VDD_X = 2.9 V

0B 0 x x x x 0 0 1 VDD_RF = 2.8 V, VDD_A = 2.8 V, VDD_X = 2.8 V

0B 0 x x x x 0 0 0 VDD_RF = 2.7 V, VDD_A = 2.7 V, VDD_X = 2.7 V

The regulator configuration function adjusts the regulator outputs by default to 250 mV below VIN level,

but not higher than 5 V for VDD_RF, 3.4 V for VDD_A and VDD_X. This ensures the highest possible

supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection

ratio).

To further improve the PSRR, it is possible to increase the target voltage difference across VDD_X and

VDD_A from its default to 350 mV or even 400 mV (for details, see Regulator and I/O Control register

0x0B definition and Table 6-2.)

6.5 Power Modes

The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits

in the Chip Status Control register (0x00).

Table 6-3 lists the configuration for the different power modes when using a 5-V or 3-V system supply.

The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled,

the 13.56-MHz oscillator is running, and the SYS_CLK (output clock for external microcontroller) is also

available.

The Regulator Control register settings shown are for optimized power out. The automatic setting

(normally 0x87) is optimized for best PSRR and noise reduction.

TRF7960A

ZHCS266F –JUNE 2011 –REVISED MAY 2017

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The input pin EN2 has two functions:

• A direct connection from EN2 to VIN to ensure the availability of the regulated supply VDD_X and an

auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is

intended for systems in which the MCU is also being supplied by the reader supply regulator (VDD_X)

and the MCU clock is supplied by the SYS_CLK output of the reader. This lets the MCU supply and

clock be available during sleep mode.

• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this

case, the EN input is being controlled by the MCU (or other system device) that is without supply

voltage during complete power down (thus unable to control the EN input). A rising edge applied to the

EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and

13.56‑MHz oscillator (identical to condition EN = 1).

When the user MCU controls EN and EN2, use a delay of 5 ms between EN and EN2. When the MCU

controls only EN, TI recommends connecting EN2 to either VIN or GND, depending on the application

MCU requirements for VDD_X and SYS_CLK.

NOTE

Using EN = 1 and EN2 = 1 in parallel at start-up should not be done as it may cause

incorrect operation.

This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized.

If the EN input is set high (EN = 1) by the MCU (or other system device), the reader stays active. If the EN

input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock

(60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to

complete Power-Down Mode 1. This option can be used to wake the reader system from complete power

down (PD Mode 1) by using a push-button switch or by sending a single pulse.

After the reader EN line is high, the other power modes are selected by control bits within the Chip Status

Control register (0x00). The power mode options and states are listed in Table 6-3.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are

activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency

is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56-MHz

frequency derived from the crystal oscillator. At this time, the reader is ready to communicate and perform

the required tasks. The MCU can then program the Chip Status Control register 0x00 and select the

operation mode by programming the additional registers.

• Standby mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in

100 µ s.

• Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low-power

mode that lets the reader recover to full operation within 25 µs.

• Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to

measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader

anticollision is implemented.

• Mode 3 and Mode 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the

modes used for typical transmit and receive operations.

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